Patents by Inventor Haruo Amada
Haruo Amada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8492176Abstract: To provide a method of manufacturing a semiconductor device including a step of attaching a surface protective tape onto the surface of a wafer which has completed the wafer process, a step of subjecting the back surface of the wafer to back grinding, and a step of attaching a peeling assist tape onto the surface protective tape while vacuum-adsorbing the back surface of the wafer to apply a tension to the assist tape, thereby separating the surface protective tape from the wafer, wherein a vacuum suction system has a peripheral suction system for the peripheral part of the wafer and an internal suction system for the internal region of the wafer.Type: GrantFiled: September 11, 2012Date of Patent: July 23, 2013Assignee: Renesas Electronics CorporationInventor: Haruo Amada
-
Publication number: 20130089970Abstract: To provide a method of manufacturing a semiconductor device including a step of attaching a surface protective tape onto the surface of a wafer which has completed the wafer process, a step of subjecting the back surface of the wafer to back grinding, and a step of attaching a peeling assist tape onto the surface protective tape while vacuum-adsorbing the back surface of the wafer to apply a tension to the assist tape, thereby separating the surface protective tape from the wafer, wherein a vacuum suction system has a peripheral suction system for the peripheral part of the wafer and an internal suction system for the internal region of the wafer.Type: ApplicationFiled: September 11, 2012Publication date: April 11, 2013Applicant: Renesas Electronics CorporationInventor: Haruo AMADA
-
Patent number: 8153452Abstract: The semiconductor device is formed by forming a first metal film over a first main surface of a semiconductor wafer having a first thickness, performing back grinding to a second main surface of the semiconductor wafer thereby making a second thickness thinner than the first thickness and forming an insulation film pattern having a first insulation film and containing an annular insulation film pattern along the periphery of a second main surface of the semiconductor wafer over the second main surface along the periphery thereof. The second main surface of the semiconductor wafer is bonded to a pressure sensitive adhesive sheet thereby holding the device semiconductor wafer by way of the pressure sensitive adhesive sheet to a dicing frame in a state where the insulation film pattern is present.Type: GrantFiled: September 20, 2011Date of Patent: April 10, 2012Assignee: Renesas Electronics CorporationInventors: Haruo Amada, Kenji Shimazawa
-
Publication number: 20120009695Abstract: The semiconductor device is formed by forming a first metal film over a first main surface of a semiconductor wafer having a first thickness, performing back grinding to a second main surface of the semiconductor wafer thereby making a second thickness thinner than the first thickness and forming an insulation film pattern having a first insulation film and containing an annular insulation film pattern along the periphery of a second main surface of the semiconductor wafer over the second main surface along the periphery thereof. The second main surface of the semiconductor wafer is bonded to a pressure sensitive adhesive sheet thereby holding the device semiconductor wafer by way of the pressure sensitive adhesive sheet to a dicing frame in a state where the insulation film pattern is present.Type: ApplicationFiled: September 20, 2011Publication date: January 12, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Haruo Amada, Kenji Shimazawa
-
Patent number: 8039276Abstract: The semiconductor device si formed by forming a first metal film over a first main surface of a semiconductor wafer having a first thinkness, performing back grinding to a second main surface of the semiconductor wafer thereby making a second thickness thinner than the first thickness and forming an insulation film pattern having a first insulation film and containing an annular insulation film pattern along the periphery of a second main surface of the semiconductor wafer over the second main surface along the periphery thereof. The second main surface of the semiconductor wafer is bonded to a pressure sensitive adhesive sheet thereby holding the device semiconductor wafer by way of the pressure sensitive adhesive sheet to a dicing frame in a state where the insulation film pattern is present.Type: GrantFiled: March 8, 2010Date of Patent: October 18, 2011Assignee: Renesas Electronics CorporationInventors: Haruo Amada, Kenji Shimazawa
-
Publication number: 20110212609Abstract: Provided is a technology capable of improving a production yield of a semiconductor device having, for example, IGBG as a semiconductor element. After formation of an interconnect on the surface side of a semiconductor substrate, a supporting substrate covering the interconnect is bonded onto the interconnect. Then, a BG tape is overlapped and bonded onto the supporting substrate and the semiconductor substrate is ground from the backside. The BG tape is then peeled off and an impurity is introduced into the backside of the semiconductor substrate by ion implantation. Then, the supporting substrate is peeled off, followed by heat treatment of the semiconductor substrate.Type: ApplicationFiled: May 6, 2011Publication date: September 1, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Hidekazu Okuda, Haruo Amada, Taizo Hashimoto
-
Patent number: 7977165Abstract: Provided is a technology capable of improving a production yield of a semiconductor device having, for example, IGBG as a semiconductor element. After formation of an interconnect on the surface side of a semiconductor substrate, a supporting substrate covering the interconnect is bonded onto the interconnect. Then, a BG tape is overlapped and bonded onto the supporting substrate and the semiconductor substrate is ground from the backside. The BG tape is then peeled off and an impurity is introduced into the backside of the semiconductor substrate by ion implantation. Then, the supporting substrate is peeled off, followed by heat treatment of the semiconductor substrate.Type: GrantFiled: December 22, 2009Date of Patent: July 12, 2011Assignee: Renesas Electronics CorporationInventors: Hidekazu Okuda, Haruo Amada, Taizo Hashimoto
-
Publication number: 20100267175Abstract: In a process for a semiconductor typically represented by a vertical power MOSFET, etc. of repeating various fabrications in a state of a thin film wafer with the thickness of the wafer being 200 ?m or less, it is a standard procedure of conducting processing in a stage of bonding a reinforcing glass sheet to a device surface of the wafer (main surface on the side of surface) in the step after film thickness-reduction. However according to the study of the present inventors, it has been found that about 70% for the manufacturing cost is concerned with the reinforcing glass sheet. In the present invention, a stress relief insulation film pattern is formed to the peripheral end of the rear face of a wafer in which processing to the device surface (surface side face) of the wafer has been completed substantially and back grinding has been applied.Type: ApplicationFiled: March 8, 2010Publication date: October 21, 2010Applicant: RENESAS TECHNOLOGY CORP.Inventors: Haruo AMADA, Kenji SHIMAZAWA
-
Publication number: 20100127306Abstract: Provided is a technology capable of improving a production yield of a semiconductor device having, for example, IGBG as a semiconductor element. After formation of an interconnect on the surface side of a semiconductor substrate, a supporting substrate covering the interconnect is bonded onto the interconnect. Then, a BG tape is overlapped and bonded onto the supporting substrate and the semiconductor substrate is ground from the backside. The BG tape is then peeled off and an impurity is introduced into the backside of the semiconductor substrate by ion implantation. Then, the supporting substrate is peeled off, followed by heat treatment of the semiconductor substrate.Type: ApplicationFiled: December 22, 2009Publication date: May 27, 2010Applicant: RENESAS TECHNOLOGY CORP.Inventors: Hidekazu Okuda, Haruo Amada, Taizo Hashimoto
-
Patent number: 7687907Abstract: Provided is a technology capable of improving a production yield of a semiconductor device having, for example, IGBG as a semiconductor element. After formation of an interconnect on the surface side of a semiconductor substrate, a supporting substrate covering the interconnect is bonded onto the interconnect. Then, a BG tape is overlapped and bonded onto the supporting substrate and the semiconductor substrate is ground from the backside. The BG tape is then peeled off and an impurity is introduced into the backside of the semiconductor substrate by ion implantation. Then, the supporting substrate is peeled off, followed by heat treatment of the semiconductor substrate.Type: GrantFiled: December 28, 2007Date of Patent: March 30, 2010Assignee: Renesas Technology Corp.Inventors: Hidekazu Okuda, Haruo Amada, Taizo Hashimoto
-
Publication number: 20080105971Abstract: Provided is a technology capable of improving a production yield of a semiconductor device having, for example, IGBG as a semiconductor element. After formation of an interconnect on the surface side of a semiconductor substrate, a supporting substrate covering the interconnect is bonded onto the interconnect. Then, a BG tape is overlapped and bonded onto the supporting substrate and the semiconductor substrate is ground from the backside. The BG tape is then peeled off and an impurity is introduced into the backside of the semiconductor substrate by ion implantation. Then, the supporting substrate is peeled off, followed by heat treatment of the semiconductor substrate.Type: ApplicationFiled: December 28, 2007Publication date: May 8, 2008Inventors: Hidekazu OKUDA, Haruo Amada, Taizo Hashimoto
-
Patent number: 7335574Abstract: Provided is a technology capable of improving a production yield of a semiconductor device having, for example, IGBG as a semiconductor element. After formation of an interconnect on the surface side of a semiconductor substrate, a supporting substrate covering the interconnect is bonded onto the interconnect. Then, a BG tape is overlapped and bonded onto the supporting substrate and the semiconductor substrate is ground from the backside. The BG tape is then peeled off and an impurity is introduced into the backside of the semiconductor substrate by ion implantation. Then, the supporting substrate is peeled off, followed by heat treatment of the semiconductor substrate.Type: GrantFiled: April 7, 2005Date of Patent: February 26, 2008Assignee: Renesas Technology Corp.Inventors: Hidekazu Okuda, Haruo Amada, Taizo Hashimoto
-
Publication number: 20050233499Abstract: Provided is a technology capable of improving a production yield of a semiconductor device having, for example, IGBG as a semiconductor element. After formation of an interconnect on the surface side of a semiconductor substrate, a supporting substrate covering the interconnect is bonded onto the interconnect. Then, a BG tape is overlapped and bonded onto the supporting substrate and the semiconductor substrate is ground from the backside. The BG tape is then peeled off and an impurity is introduced into the backside of the semiconductor substrate by ion implantation. Then, the supporting substrate is peeled off, followed by heat treatment of the semiconductor substrate.Type: ApplicationFiled: April 7, 2005Publication date: October 20, 2005Inventors: Hidekazu Okuda, Haruo Amada, Taizo Hashimoto
-
Patent number: 5857661Abstract: A valve drive control apparatus having a communication unit for communicating a flow-in-side tube path with a flow-out-side tube path, which guide a fluid member, and a control medium storage chamber into which an attenuation characteristic control medium is filled. The valve drive control apparatus further includes an elastic deform member for defining the communication unit and the control medium storage chamber, a drive unit for pressuring the attenuation characteristic control medium so as to deform the elastic deform member via the attenuation characteristic control medium, and also a control unit for controlling the drive unit based on a drive control valve obtained from a valve drive characteristic representative of a relationship between a deform amount of a valve mechanism unit and a drive pressure value of the valve mechanism unit.Type: GrantFiled: October 30, 1995Date of Patent: January 12, 1999Assignees: Hitachi, Ltd., Koganei CorporationInventors: Haruo Amada, Takashi Komatsu
-
Patent number: 5134962Abstract: The present invention relates to a spin coating apparatus for feeding a clean liquid at a fixed rate. In any of the feeding apparatus in the prior art, no constituent other than a filter has the function of eliminating foreign matter, and the operation of feeding a liquid under precise control is not attained. This results in the problem of the mixing of the foreign matter (and air bubbles) in the feed liquid, and the problem of nonuniformity in a feed speed as well as a feed amount. As expedients for solving these problems, the present invention provides the functions of automatically sensing and excluding factors for the appearances of the foreign matters, and devices for automatically and precisely controlling feed control elements such as a pump, thereby feeding the clean liquid in a constant amount and at a constant speed.Type: GrantFiled: May 16, 1990Date of Patent: August 4, 1992Assignees: Hitachi, Ltd., CKD CorporationInventors: Haruo Amada, Akihiro Kojima, Hiroshi Kagohashi, Atsuyuki Sakai, Katsumasa Shimura, Hisamitsu Maekawa
-
Patent number: 4667076Abstract: The present invention relates to a method of heat-treating a semiconductor wafer by utilizing an electromagnetic wave. The wafer is floated by the blast of a gas and is held in a non-contacting state, and the electromagnetic wave, such as microwave, is projected on the wafer in this state so as to heat it. According to the present invention, only the wafer is heated and, hence, the wafer can be heat-treated uniformly and efficiently with great precision.Type: GrantFiled: October 2, 1985Date of Patent: May 19, 1987Assignee: Hitachi, Ltd.Inventor: Haruo Amada
-
Patent number: 4593168Abstract: The present invention relates to a method of heat-treating a semiconductor wafer by utilizing an electromagnetic wave. The wafer is floated by the blast of a gas and is held in a non-contacting state, and the electromagnetic wave, such as microwave, is projected on the wafer in this state so as to heat it. According to the present invention, only the wafer is heated and, hence, the wafer can be heat-treated uniformly and efficiently with great precision.Type: GrantFiled: February 17, 1984Date of Patent: June 3, 1986Assignee: Hitachi, Ltd.Inventor: Haruo Amada