Abstract: Disclosed is a method for manufacturing a magnetic storage device comprising a TMR element, which comprises a step for forming an insulting film on an interlayer insulating film provided with a wiring layer, an opening formation step for forming an opening in the insulating film so that the wiring layer is exposed therefrom, a metal layer formation step for forming a metal layer on the insulating layer so that the opening is filled therewith, a CMP step for polishing and removing the metal layer on the insulating layer by a CMP method and forming the metal layer remaining in the opening into a lower electrode, and a step for forming a TMR element on the lower electrode.

Abstract: A semiconductor device having a MTJ device excellent in operating characteristics and a manufacturing method therefor are provided. The MTJ device is formed of a laminated structure which is obtained by laminating a lower magnetic film, a tunnel insulating film, and an upper magnetic film in this order. The lower and upper magnetic films contain noncrystalline or microcrystalline ferrocobalt boron (CoFeB) as a constituent material. The tunnel insulating film contains aluminum oxide (AlOx) as a constituent material. A CAP layer is formed over the upper magnetic film and a hard mask is formed over the CAP layer. The CAP layer contains a substance of crystalline ruthenium (Ru) as a constituent material and the hard mask contains a substance of crystalline tantalum (Ta) as a constituent material. The film thickness of the hard mask is larger than that of the CAP layer.

Abstract: A semiconductor device having a MTJ device excellent in operating characteristics and a manufacturing method therefor are provided. The MTJ device is formed of a laminated structure which is obtained by laminating a lower magnetic film, a tunnel insulating film, and an upper magnetic film in this order. The lower and upper magnetic films contain noncrystalline or microcrystalline ferrocobalt boron (CoFeB) as a constituent material. The tunnel insulating film contains aluminum oxide (AlOx) as a constituent material. A CAP layer is formed over the upper magnetic film and a hard mask is formed over the CAP layer. The CAP layer contains a substance of crystalline ruthenium (Ru) as a constituent material and the hard mask contains a substance of crystalline tantalum (Ta) as a constituent material. The film thickness of the hard mask is larger than that of the CAP layer.

Abstract: A semiconductor device having a MTJ device excellent in operating characteristics and a manufacturing method therefor are provided. The MTJ device is formed of a laminated structure which is obtained by laminating a lower magnetic film, a tunnel insulating film, and an upper magnetic film in this order. The lower and upper magnetic films contain noncrystalline or microcrystalline ferrocobalt boron (CoFeB) as a constituent material. The tunnel insulating film contains aluminum oxide (AlOx) as a constituent material. A CAP layer is formed over the upper magnetic film and a hard mask is formed over the CAP layer. The CAP layer contains a substance of crystalline ruthenium (Ru) as a constituent material and the hard mask contains a substance of crystalline tantalum (Ta) as a constituent material. The film thickness of the hard mask is larger than that of the CAP layer.

Abstract: The semiconductor device which has a memory cell including the TMR film with which memory accuracy does not deteriorate, and its manufacturing method are obtained. A TMR element (a TMR film, a TMR upper electrode) is selectively formed in the region which corresponds in plan view on a TMR lower electrode in a part of formation area of a digit line. A TMR upper electrode is formed by 30-100 nm thickness of Ta, and functions also as a hard mask at the time of a manufacturing process. The interlayer insulation film formed from LT-SiN on the whole surface of a TMR element and the upper surface of a TMR lower electrode is formed, and the interlayer insulation film which covers the whole surface comprising the side surface of a TMR lower electrode, and includes LT-SiN is formed. The interlayer insulation film which covers the whole surface and includes SiO2 is formed.

Abstract: The semiconductor device which has a memory cell including the TMR film with which memory accuracy does not deteriorate, and its manufacturing method are obtained. A TMR element (a TMR film, a TMR upper electrode) is selectively formed in the region which corresponds in plan view on a TMR lower electrode in a part of formation area of a digit line. A TMR upper electrode is formed by 30-100 nm thickness of Ta, and functions also as a hard mask at the time of a manufacturing process. The interlayer insulation film formed from LT-SiN on the whole surface of a TMR element and the upper surface of a TMR lower electrode is formed, and the interlayer insulation film which covers the whole surface comprising the side surface of a TMR lower electrode, and includes LT-SiN is formed. The interlayer insulation film which covers the whole surface and includes SiO2 is formed.

Abstract: A method for manufacturing a magnetic memory device which includes a TMR element, and the method includes: a step of forming a lower wiring layer; a step of forming an interlayer insulating layer on the lower wiring layer; a step of forming an opening in the interlayer insulating layer so that the lower wiring layer is exposed; a step of forming a barrier metal layer so that the interlayer insulating layer and an inner surface of the opening are covered; a step of forming a metal layer on the barrier metal layer so that the opening is embedded; a polishing step of removing the metal layer on the barrier metal layer through polishing using the barrier metal layer as a stopper so that a wiring layer that includes a metal layer being embedded in the opening and the barrier metal layer is formed; and an element fabricating step of fabricating a TMR element on the wiring layer.

Abstract: A method for manufacturing a magnetic memory device which includes a TMR element, and the method includes: a step of forming a lower wiring layer; a step of forming an interlayer insulating layer on the lower wiring layer; a step of forming an opening in the interlayer insulating layer so that the lower wiring layer is exposed; a step of forming a barrier metal layer so that the interlayer insulating layer and an inner surface of the opening are covered; a step of forming a metal layer on the barrier metal layer so that the opening is embedded; a polishing step of removing the metal layer on the barrier metal layer through polishing using the barrier metal layer as a stopper so that a wiring layer that includes a metal layer being embedded in the opening and the barrier metal layer is formed; and an element fabricating step of fabricating a TMR element on the wiring layer.

Abstract: Disclosed is a method for manufacturing a magnetic storage device comprising a TMR element, which comprises a step for forming an insulting film on an interlayer insulating film provided with a wiring layer, an opening formation step for forming an opening in the insulating film so that the wiring layer is exposed therefrom, a metal layer formation step for forming a metal layer on the insulating layer so that the opening is filled therewith, a CMP step for polishing and removing the metal layer on the insulating layer by a CMP method and forming the metal layer remaining in the opening into a lower electrode, and a step for forming a TMR element on the lower electrode.

Abstract: The semiconductor device which has a memory cell including the TMR film with which memory accuracy does not deteriorate, and its manufacturing method are obtained. A TMR element (a TMR film, a TMR upper electrode) is selectively formed in the region which corresponds in plan view on a TMR lower electrode in a part of formation area of a digit line. A TMR upper electrode is formed by 30-100 nm thickness of Ta, and functions also as a hard mask at the time of a manufacturing process. The interlayer insulation film formed from LT-SiN on the whole surface of a TMR element and the upper surface of a TMR lower electrode is formed, and the interlayer insulation film which covers the whole surface comprising the side surface of a TMR lower electrode, and includes LT-SiN is formed. The interlayer insulation film which covers the whole surface and includes SiO2 is formed.

Abstract: A semiconductor device having an MTJ device excellent in operating characteristics and a manufacturing method therefor are obtained. The MTJ device is formed of a laminated structure obtained by laminating a lower magnetic film, a tunnel insulating film, and an upper magnetic film in this order. The lower magnetic film and the upper magnetic film contain noncrystalline or microcrystalline ferrocobalt boron (CoFeB) as a constituent material. The tunnel insulating film contains aluminum oxide (AlOx) as a constituent material. A CAP layer is formed over the upper magnetic film of the MTJ device and a hard mask is formed over the CAP layer. The CAP layer contains a simple substance of crystalline ruthenium (Ru) as a constituent material and the hard mask contains a simple substance of crystalline tantalum (Ta) as a constituent material. The hard mask is so formed that the film thickness thereof is larger than the film thickness of the CAP layer.

Abstract: The semiconductor device which has a memory cell including the TMR film with which memory accuracy does not deteriorate, and its manufacturing method are obtained. A TMR element (a TMR film, a TMR upper electrode) is selectively formed in the region which corresponds in plan view on a TMR lower electrode in a part of formation area of a digit line. A TMR upper electrode is formed by 30-100 nm thickness of Ta, and functions also as a hard mask at the time of a manufacturing process. The interlayer insulation film formed from LT-SiN on the whole surface of a TMR element and the upper surface of a TMR lower electrode is formed, and the interlayer insulation film which covers the whole surface comprising the side surface of a TMR lower electrode, and includes LT-SiN is formed. The interlayer insulation film which covers the whole surface and includes SiO2 is formed.

Abstract: A width and a thickness of a bit line are represented as W1 and T1, respectively, a thickness of a digit line is represented as T2, and a distance from a center of the digit line in a thickness direction to a center of a free layer of an MTJ element in the thickness direction is represented as L1. A width of the digit line is represented as W2, and a distance from a center of the bit line in the thickness direction to the center of the free layer of the MTJ element in the thickness direction is represented as L2. The distances L1 and L2 and the cross-sectional areas S1 and S2 are set in such a manner that when L1/L2?1, a relation of (1/3)·(L1/L2)?S2/S1?1 is satisfied and when L1/L2?1, a relation of 1?S2/S1?3(L1/L2) is satisfied.

Abstract: A width and a thickness of a bit line are represented as W1 and T1, respectively, a thickness of a digit line is represented as T2, and a distance from a center of the digit line in a thickness direction to a center of a free layer of an MTJ element in the thickness direction is represented as L1. A width of the digit line is represented as W2, and a distance from a center of the bit line in the thickness direction to the center of the free layer of the MTJ element in the thickness direction is represented as L2. The distances L1 and L2 and the cross-sectional areas S1 and S2 are set in such a manner that when L1/L2?1, a relation of (?)·(L1/L2)?S2/S1?1 is satisfied and when L1/L2?1, a relation of 1?S2/S1?3(L1/L2) is satisfied.

Abstract: A method for manufacturing a magnetic memory device which includes a TMR element, and the method includes: a step of forming a lower wiring layer; a step of forming an interlayer insulating layer on the lower wiring layer; a step of forming an opening in the interlayer insulating layer so that the lower wiring layer is exposed; a step of forming a barrier metal layer so that the interlayer insulating layer and an inner surface of the opening are covered; a step of forming a metal layer on the barrier metal layer so that the opening is embedded; a polishing step of removing the metal layer on the barrier metal layer through polishing using the barrier metal layer as a stopper so that a wiring layer that includes a metal layer being embedded in the opening and the barrier metal layer is formed; and an element fabricating step of fabricating a TMR element on the wiring layer.

Abstract: A width and a thickness of a bit line are represented as W1 and T1, respectively, a thickness of a digit line is represented as T2, and a distance from a center of the digit line in a thickness direction to a center of a free layer of an MTJ element in the thickness direction is represented as L1. A width of the digit line is represented as W2, and a distance from a center of the bit line in the thickness direction to the center of the free layer of the MTJ element in the thickness direction is represented as L2. The distances L1 and L2 and the cross-sectional areas S1 and S2 are set in such a manner that when L1/L2?1, a relation of (?)·(L1/L2)?S2/S1?1 is satisfied and when L1/L2?1, a relation of 1?S2/S1?3(L1/L2) is satisfied.

Abstract: A width and a thickness of a bit line are represented as W1 and T1, respectively, a thickness of a digit line is represented as T2, and a distance from a center of the digit line in a thickness direction to a center of a free layer of an MTJ element in the thickness direction is represented as L1. A width of the digit line is represented as W2, and a distance from a center of the bit line in the thickness direction to the center of the free layer of the MTJ element in the thickness direction is represented as L2. The distances L1 and L2 and the cross-sectional areas S1 and S2 are set in such a manner that when L1/L2?1, a relation of (?)·(L1/L2 )?S2/S1?1 is satisfied and when L1/L2?1, a relation of 1?S2/S1?3(L1 /L2) is satisfied.

Abstract: It is an object to provide a semiconductor device capable of holding multibit information in one memory cell also when scaling for a nonvolatile memory progresses, and a method of manufacturing the semiconductor device. A trench (TRI) is formed in a channel portion of an MONOS transistor. Then, a source side portion and a drain side portion in a silicon nitride film (122) of a gate insulating film (120) which interpose the trench (TR1) are caused to function as first and second electric charge holding portions capable of holding electric charges (CH1) and (CH2). In the case in which the electric charges (CH1) are trapped and the electric charges (CH2) are then trapped, thus, a portion (130a) of a gate electrode (130) in the trench (TR1) functions as a shield. If a fixed potential is given to the gate electrode (130), the second electric charge holding portion is not influenced by an electric field (EF1) induced by the electric charges (CH1) so that the trapping of the electric charges (CH2) is not inhibited.

Abstract: A width and a thickness of a bit line are represented as W1 and T1, respectively, a thickness of a digit line is represented as T2, and a distance from a center of the digit line in a thickness direction to a center of a free layer of an MTJ element in the thickness direction is represented as L1. A width of the digit line is represented as W2, and a distance from a center of the bit line in the thickness direction to the center of the free layer of the MTJ element in the thickness direction is represented as L2. The distances L1 and L2 and the cross-sectional areas S1 and S2 are set in such a manner that when L1/L2?1, a relation of (1/3)·(L1/L2)?S2/S1?1 is satisfied and when L1/L2?1, a relation of 1?S2/S1?3(L1/L2) is satisfied.

Abstract: The semiconductor device which has a memory cell including the TMR film with which memory accuracy does not deteriorate, and its manufacturing method are obtained. A TMR element (a TMR film, a TMR upper electrode) is selectively formed in the region which corresponds in plan view on a TMR lower electrode in a part of formation area of a digit line. A TMR upper electrode is formed by 30-100 nm thickness of Ta, and functions also as a hard mask at the time of a manufacturing process. The interlayer insulation film formed from LT-SiN on the whole surface of a TMR element and the upper surface of a TMR lower electrode is formed, and the interlayer insulation film which covers the whole surface comprising the side surface of a TMR lower electrode, and includes LT-SiN is formed. The interlayer insulation film which covers the whole surface and includes SiO2 is formed.