Patents by Inventor Haruo Hyoudo
Haruo Hyoudo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 6784523Abstract: An object of the present invention is to provide a method of fabricating a semiconductor device having a relatively small package structure and hence a relatively small mounting area. Another object of the present invention is to provide a method of fabricating a semiconductor device relatively inexpensively. An insulating board with a plurality of device carrier areas thereon is prepared, and islands and leads are formed on the device carrier areas electrically connected via through holes to external electrodes on the back of the insulating board. The external electrodes are spaced or retracted inwardly from edges of the device carrier areas. Semiconductor chips are mounted on the respective device carrier areas by die bonding and wire bonding, and then covered with a common resin layer. The resin layer and the insulating board are separated along cutting lines into segments including the device carrier areas thereby to produce individual semiconductor devices.Type: GrantFiled: October 12, 2001Date of Patent: August 31, 2004Assignee: Sanyo Electric Co., Ltd.Inventors: Takayuki Tani, Haruo Hyoudo, Takao Shibuya
-
Patent number: 6521482Abstract: A method of manufacturing individual semiconductor devices by forming island sections 26 on the surface of a common substrate 21, forming electrodes 27 and 28 one on either side of each island section 26, die bonding a semiconductor chip 29 to each island section 26, and wire bonding the electrodes 27 and 28 to the semiconductor chip 29. A single common cover 36 is fixed over the entire surface of the common substrate 21 to form a hermetically sealed hollow space over each chip mounting section 41. The cover 36 and substrate 21 are separated at each mounting section 41 to form individual semiconductor devices.Type: GrantFiled: August 3, 2000Date of Patent: February 18, 2003Assignee: Sanyo Electric Co., Ltd.Inventors: Haruo Hyoudo, Shigeo Kimura, Takanori Shibasaki
-
Patent number: 6511864Abstract: An object of the present invention is to provide a method of fabricating a semiconductor device having a relatively small package structure and hence a relatively small mounting area. An insulating board with a plurality of device carrier areas thereon is prepared, and semiconductor chips are mounted on the respective device carrier areas and then covered with a common resin layer. The resin layer and said insulating board are separated along dicing lines into segments including the device carrier areas thereby to produce individual semiconductor devices. External electrodes connected to electrodes of the semiconductor chips are mounted on the back of the insulating board. The external electrodes are positioned symmetrically with respect to central lines of the packaged semiconductor device for preventing various problems which would otherwise be caused when such a small package is mounted.Type: GrantFiled: August 28, 2001Date of Patent: January 28, 2003Assignee: Sanyo Electric Co., Ltd.Inventors: Haruo Hyoudo, Takayuki Tani, Takao Shibuya
-
Patent number: 6461893Abstract: In producing an electronic device such as an overcurrent-protection element, a large substrate 21 is prepared with a plurality of element mounting sections 50. Electrodes 25 and 26 are formed on the surface of the substrate 21 in each of the element mounting sections 50. A fine metal wire 27 is connected between the electrodes 25 and 26 to form a fuse element. A framework portion 41 surrounds each element mounting section 50, forming a depression 24. The depression 24 houses the fine metal wire 27. A cover member 31 is placed over the top of the framework 41, hermetically sealing the depressions 24. Subsequently, the cover member 31 and substrate 21 are cut together, separating each of the element mounting sections 50 to obtain individual electronic devices.Type: GrantFiled: June 7, 2001Date of Patent: October 8, 2002Assignee: Sanyo Electric Co., Ltd.Inventors: Haruo Hyoudo, Shigeo Kimura
-
Publication number: 20020081769Abstract: The object of the present invention is to provide a semiconductor device having small mounting area with reduced cost.Type: ApplicationFiled: February 25, 2002Publication date: June 27, 2002Inventors: Takayuki Tani, Haruo Hyoudo, Takao Shibuya
-
Patent number: 6368893Abstract: A method of fabricating a semiconductor device including preparing a board with a plurality of device carrier areas thereon and an electrode pattern serving as external electrodes on a back of the board. Semiconductor chips are fixed respectively to the device carrier areas. The semiconductor chips fixed to the device carrier areas are covered with a common resin layer. A round surface of the common resin layer is flattened into a flat and horizontal surface, and a dicing sheet is applied to the flat and horizontal surface of the common resin layer with electrode pattern facing upwardly. The board and the common resin layer are separated into segments including the device carrier areas thereby to produce individual semiconductor devices by dicing from the back of the board.Type: GrantFiled: February 9, 2000Date of Patent: April 9, 2002Assignee: Sanyo Electric Co., Ltd.Inventors: Takayuki Tani, Haruo Hyoudo, Takao Shibuya
-
Patent number: 6365433Abstract: A semiconductor device having an overcurrent protection element therein is provided. The device comprises: a substrate having first and second main surfaces; a semiconductor chip fixed to the first main surface of the substrate; a fuse element fixed to the first main surface of the substrate; a cover member fixed to the substrate for sealing the semiconductor chip and the fuse element in an airtight space; and external connecting terminals formed on the second main surface of the substrate.Type: GrantFiled: April 25, 2000Date of Patent: April 2, 2002Assignee: Sanyo Electric Co., Ltd.Inventors: Haruo Hyoudo, Shigeo Kimura
-
Publication number: 20020022302Abstract: An object of the present invention is to provide a method of fabricating a semiconductor device having a relatively small package structure and hence a relatively small mounting area.Type: ApplicationFiled: August 28, 2001Publication date: February 21, 2002Inventors: Haruo Hyoudo, Takayuki Tani, Takao Shibuya
-
Publication number: 20020022312Abstract: An object of the present invention is to provide a method of fabricating a semiconductor device having a relatively small package structure and hence a relatively small mounting area. Another object of the present invention is to provide a method of fabricating a semiconductor device relatively inexpensively. An insulating board with a plurality of device carrier areas thereon is prepared, and islands and leads are formed on the device carrier areas electrically connected via through holes to external electrodes on the back of the insulating board. The external electrodes are spaced or retracted inwardly from edges of the device carrier areas. Semiconductor chips are mounted on the respective device carrier areas by die bonding and wire bonding, and then covered with a common resin layer. The resin layer and the insulating board are separated along cutting lines into segments including the device carrier areas thereby to produce individual semiconductor devices.Type: ApplicationFiled: October 12, 2001Publication date: February 21, 2002Inventors: Takayuki Tani, Haruo Hyoudo, Takao Shibuya
-
Patent number: 6326232Abstract: An object of the present invention is to provide a method of fabricating a semiconductor device having a relatively small package structure and hence a relatively small mounting area. Another object of the present invention is to provide a method of fabricating a semiconductor device relatively inexpensively. An insulating board with a plurality of device carrier areas thereon is prepared, and islands and leads are formed on the device carrier areas electrically connected via through holes to external electrodes on the back of the insulating board. The external electrodes are spaced or retracted inwardly from edges of the device carrier areas. Semiconductor chips are mounted on the respective device carrier areas by die bonding and wire bonding, and then covered with a common resin layer. The resin layer and the insulating board are separated along cutting lines into segments including the device carrier areas thereby to produce individual semiconductor devices.Type: GrantFiled: November 17, 1999Date of Patent: December 4, 2001Assignee: Sanyo Electric Co., Ltd.Inventors: Takayuki Tani, Haruo Hyoudo, Takao Shibuya
-
Publication number: 20010042898Abstract: In producing an electronic device such as an overcurrent-protection element, a large substrate 21 is prepared with a plurality of element mounting sections 50. Electrodes 25 and 26 are formed on the surface of the substrate 21 in each of the element mounting sections 50. A fine metal wire 27 is connected between the electrodes 25 and 26 to form a fuse element. A framework portion 41 surrounds each element mounting section 50, forming a depression 24. The depression 24 houses the fine metal wire 27. A cover member 31 is placed over the top of the framework 41, hermetically sealing the depressions 24. Subsequently, the cover member 31 and substrate 21 are cut together, separating each of the element mounting sections 50 to obtain individual electronic devices.Type: ApplicationFiled: June 7, 2001Publication date: November 22, 2001Inventors: Haruo Hyoudo, Shigeo Kimura
-
Patent number: 6309911Abstract: An object of the present invention is to provide a method of fabricating a semiconductor device having a relatively small package structure and hence a relatively small mounting area. An insulating board with a plurality of device carrier areas thereon is prepared, and semiconductor chips are mounted on the respective device carrier areas and then covered with a common resin layer. The resin layer and said insulating board are separated along dicing lines into segments including the device carrier areas thereby to produce individual semiconductor devices. External electrodes connected to electrodes of the semiconductor chips are mounted on the back of the insulating board. The external electrodes are positioned symmetrically with respect to central lines of the packaged semiconductor device for preventing various problems which would otherwise be caused when such a small package is mounted.Type: GrantFiled: January 29, 2001Date of Patent: October 30, 2001Assignee: Sanyo Electric Co., Ltd.Inventors: Haruo Hyoudo, Takayuki Tani, Takao Shibuya
-
Patent number: 6285067Abstract: In producing an electronic device such as an overcurrent-protection element, a large substrate 21 is prepared with a plurality of element mounting sections 50. Electrodes 25 and 26 are formed on the surface of the substrate 21 in each of the element mounting sections 50. A fine metal wire 27 is connected between the electrodes 25 and 26 to form a fuse element. A framework portion 41 surrounds each element mounting section 50, forming a depression 24. The depression 24 houses the fine metal wire 27. A cover member 31 is placed over the top of the framework 41, hermetically sealing the depressions 24. Subsequently, the cover member 31 and substrate 21 are cut together, separating each of the element mounting sections 50 to obtain individual electronic devices.Type: GrantFiled: April 25, 2000Date of Patent: September 4, 2001Assignee: Sanyo Electric Co., Ltd.Inventors: Haruo Hyoudo, Shigeo Kimura
-
Publication number: 20010003055Type: ApplicationFiled: January 29, 2001Publication date: June 7, 2001Inventors: Haruo Hyoudo, Takayuki Tani, Takao Shibuya
-
Patent number: 6197616Abstract: An object of the present invention is to provide a method of fabricating a semiconductor device having a relatively small package structure and hence a relatively small mounting area. An insulating board with a plurality of device carrier areas thereon is prepared, and semiconductor chips are mounted on the respective device carrier areas and then covered with a common resin layer. The resin layer and said insulating board are separated along dicing lines into segments including the device carrier areas thereby to produce individual semiconductor devices. External electrodes connected to electrodes of the semiconductor chips are mounted on the back of the insulating board. The external electrodes are positioned symmetrically with respect to central lines of the packaged semiconductor device for preventing various problems which would otherwise be caused when such a small package is mounted.Type: GrantFiled: November 24, 1999Date of Patent: March 6, 2001Assignee: Sanyo Electric Co., Ltd.Inventors: Haruo Hyoudo, Takayuki Tani, Takao Shibuya