Patents by Inventor Haruo Iwasaki

Haruo Iwasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11468184
    Abstract: A data protection system includes a data storage apparatus and an information processing apparatus. In the information processing apparatus, a redirection processing apparatus sets a personal storage area corresponding to a user to an accessible state according to a redirection policy. Furthermore, a write control unit controls data writing permission/prohibition for each storage area according to a write management policy. In particular, the write control unit prohibits data writing to a local storage unit except for the storage area to be used to access the personal storage area. With this, the data does not remain in the information processing apparatus, thereby preventing data leakage from the information processing apparatus.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: October 11, 2022
    Assignees: KYUSHU ELECTRIC POWER CO., INC., HUMMING HEADS, INC.
    Inventors: Daijiro Kariu, Naoyuki Oe, Haruo Iwasaki, Takahiro Shima
  • Publication number: 20200226273
    Abstract: A data protection system includes a data storage apparatus and an information processing apparatus. In the information processing apparatus, a redirection processing apparatus sets a personal storage area corresponding to a user to an accessible state according to a redirection policy. Furthermore, a write control unit controls data writing permission/prohibition for each storage area according to a write management policy. In particular, the write control unit prohibits data writing to a local storage unit except for the storage area to be used to access the personal storage area. With this, the data does not remain in the information processing apparatus, thereby preventing data leakage from the information processing apparatus.
    Type: Application
    Filed: August 7, 2018
    Publication date: July 16, 2020
    Inventors: Daijiro KARIU, Naoyuki OE, Haruo IWASAKI, Takahiro SHIMA
  • Patent number: 6864021
    Abstract: The invention relates to a photomask for use in a thermal flow process in which: a photomask is prepared in which a plurality of exposure openings are formed; a resist is applied to the surface of a layer of a semiconductor integrated circuit that is to undergo processing; this resist is patterned by an exposure process through the photomask to form a plurality of openings in the resist that correspond to each of the exposure openings; and the patterned resist is then heated to cause each of the openings to shrink; wherein at least a portion of exposure openings among the plurality of exposure openings are formed in shapes that compensate for anisotropic deformation that occurs in the openings when the patterned resist is heated to cause each of the openings to shrink. Since the openings that are formed in the resist are provided in advance with shapes that compensate for the deformation that occurs when the openings shrink, these openings attain the proper shape after undergoing shrinking and deformation.
    Type: Grant
    Filed: January 13, 2003
    Date of Patent: March 8, 2005
    Assignee: NEC Electronics Corporation
    Inventors: Haruo Iwasaki, Shinji Ishida, Tsuyoshi Yoshii
  • Patent number: 6841318
    Abstract: Levenson masks capable of minimizing the effect of optical proximity, and a method for forming a fine pattern using such Levenson masks wherein the Levenson masks have patterns where shielding regions are sandwiched between shifter regions and non-shifter regions respectively. The shifter regions and the non-shifter regions are formed to have predetermined shapes to minimize the effect of optical proximity. Specifically, aperture widths, which are defined as widths of the shifter regions and widths of the non-shifter regions perpendicular to the longitudinal directions of the linear shielding regions, are of a predetermined width for minimizing the effect of optical proximity. The Levenson masks have patterns different from each other and are used for multiple exposures.
    Type: Grant
    Filed: October 22, 2002
    Date of Patent: January 11, 2005
    Assignee: NEC Electronics Corporation
    Inventor: Haruo Iwasaki
  • Publication number: 20030104290
    Abstract: The invention relates to a photomask for use in a thermal flow process in which: a photomask is prepared in which a plurality of exposure openings are formed; a resist is applied to the surface of a layer of a semiconductor integrated circuit that is to undergo processing; this resist is patterned by an exposure process through the photomask to form a plurality of openings in the resist that correspond to each of the exposure openings; and the patterned resist is then heated to cause each of the openings to shrink; wherein at least a portion of exposure openings among the plurality of exposure openings are formed in shapes that compensate for anisotropic deformation that occurs in the openings when the patterned resist is heated to cause each of the openings to shrink. Since the openings that are formed in the resist are provided in advance with shapes that compensate for the deformation that occurs when the openings shrink, these openings attain the proper shape after undergoing shrinking and deformation.
    Type: Application
    Filed: January 13, 2003
    Publication date: June 5, 2003
    Inventors: Haruo Iwasaki, Shinji Ishida, Tsuyoshi Yoshii
  • Publication number: 20030104289
    Abstract: The invention relates to a photomask for use in a thermal flow process in which: a photomask is prepared in which a plurality of exposure openings are formed; a resist is applied to the surface of a layer of a semiconductor integrated circuit that is to undergo processing; this resist is patterned by an exposure process through the photomask to form a plurality of openings in the resist that correspond to each of the exposure openings; and the patterned resist is then heated to cause each of the openings to shrink; wherein at least a portion of exposure openings among the plurality of exposure openings are formed in shapes that compensate for anisotropic deformation that occurs in the openings when the patterned resist is heated to cause each of the openings to shrink. Since the openings that are formed in the resist are provided in advance with shapes that compensate for the deformation that occurs when the openings shrink, these openings attain the proper shape after undergoing shrinking and deformation.
    Type: Application
    Filed: January 13, 2003
    Publication date: June 5, 2003
    Inventors: Haruo Iwasaki, Shinji Ishida, Tsuyoshi Yoshii
  • Publication number: 20030096177
    Abstract: The present invention provides Levenson masks capable of minimizing the effect of optical proximity, and a method for forming a fine pattern using these Levenson masks.
    Type: Application
    Filed: October 22, 2002
    Publication date: May 22, 2003
    Inventor: Haruo Iwasaki
  • Patent number: 6566041
    Abstract: The invention relates to a photomask for use in a thermal flow process in which: a photomask is prepared in which a plurality of exposure openings are formed; a resist is applied to the surface of a layer of a semiconductor integrated circuit that is to undergo processing; this resist is patterned by an exposure process through the photomask to form a plurality of openings in the resist that correspond to each of the exposure openings; and the patterned resist is then heated to cause each of the openings to shrink; wherein at least a portion of exposure openings among the plurality of exposure openings are formed in shapes that compensate for anisotropic deformation that occurs in the openings when the patterned resist is heated to cause each of the openings to shrink. Since the openings that are formed in the resist are provided in advance with shapes that compensate for the deformation that occurs when the openings shrink, these openings attain the proper shape after undergoing shrinking and deformation.
    Type: Grant
    Filed: January 10, 2001
    Date of Patent: May 20, 2003
    Assignee: NEC Electronics Corporation
    Inventors: Haruo Iwasaki, Shinji Ishida, Tsuyoshi Yoshii
  • Publication number: 20030091909
    Abstract: Disclosed are a phase shift mask which has a high size precision and provides a high production yield for semiconductor devices, and a method of fabricating the same. Chrome light shielding films are formed in a predetermined pattern as light shielding films on a glass substrate, and a silicon oxide film (first phase shifter film) which has a planarized surface is formed on the entire surface of the resultant structure in such a way as to bury areas between the chrome light shielding films. A pattern of SOG (Silicon On Glass) films (second phase shifter film) is formed on the silicon oxide film. The SOG films are formed directly above the chrome light shielding films and on areas wider than the chrome light shielding films.
    Type: Application
    Filed: October 30, 2002
    Publication date: May 15, 2003
    Inventor: Haruo Iwasaki
  • Patent number: 6525353
    Abstract: An anti-reflection structure formed on a gate electrode in a MOSFET device includes a first and second anti-reflection layers sandwiching therebetween a silicon nitride layer. Each of the anti-reflection layers has a two-layer structure including a silicon oxide nitride film and a protective silicon oxide film. The anti-reflection layer structure improves the accuracy of the pattern size for the gate electrode.
    Type: Grant
    Filed: October 13, 2000
    Date of Patent: February 25, 2003
    Assignee: NEC Corporation
    Inventor: Haruo Iwasaki
  • Patent number: 6524945
    Abstract: An anti-reflection structure formed on a gate electrode in a MOSFET device includes a first and second anti-reflection layers sandwiching therebetween a silicon nitride layer. Each of the anti-reflection layers has a two-layer structure including a silicon oxide nitride film and a protective silicon oxide film. The anti-reflection layer structure improves the accuracy of the pattern size for the gate electrode.
    Type: Grant
    Filed: April 26, 2002
    Date of Patent: February 25, 2003
    Assignee: NEC Corporation
    Inventor: Haruo Iwasaki
  • Publication number: 20020197544
    Abstract: A halftone phase shift mask comprises a transparent substrate, a light shielding film formed on the transparent film for shielding exposure light, and having a first opening, and a halftone phase shift film formed in the first opening on the transparent substrate for shifting the phase of the exposure light, and having a second opening which defines an exposed region.
    Type: Application
    Filed: June 17, 2002
    Publication date: December 26, 2002
    Inventor: Haruo Iwasaki
  • Publication number: 20020177049
    Abstract: A phase-shifting mask includes (a) a substrate, (b) a light-shielding film formed on the substrate and having a plurality of first openings and a plurality of second openings, and (c) a phase-shifter formed on the substrate only in the first opening of the light-shielding film.
    Type: Application
    Filed: May 21, 2002
    Publication date: November 28, 2002
    Applicant: NEC CORPORATION
    Inventor: Haruo Iwasaki
  • Publication number: 20020119643
    Abstract: An anti-reflection structure formed on a gate electrode in a MOSFET device includes a first and second anti-reflection layers sandwiching therebetween a silicon nitride layer. Each of the anti-reflection layers has a two-layer structure including a silicon oxide nitride film and a protective silicon oxide film. The anti-reflection layer structure improves the accuracy of the pattern size for the gate electrode.
    Type: Application
    Filed: April 26, 2002
    Publication date: August 29, 2002
    Applicant: NEC CORPORATION
    Inventor: Haruo Iwasaki
  • Publication number: 20020058188
    Abstract: A Levenson phase shift mask has a phase shifter implemented by thin transparent portions and a non-phase shifter implemented by thick transparent portions, and the thin transparent portions are to be equal in transmittance to and 180 degrees different in phase from the thick transparent portions, wherein a dispersion of light intensity in optical images of the phase shifter and the non-phase shifter obtained by a CCD camera is analyzed to see whether or not the abnormal difference in transmittance and the abnormal phase difference take place, if the abnormal difference in transmittance or the abnormal phase difference takes place, the thin/thick transparent portions are reshaped so as to repair the Levenson phase shift mask.
    Type: Application
    Filed: November 14, 2001
    Publication date: May 16, 2002
    Applicant: NEC CORPORATION
    Inventors: Haruo Iwasaki, Shinji Ishida
  • Patent number: 6274427
    Abstract: A capacitor is provided, which makes it easy to increase the opposing area size between the lower and upper electrode in spite of miniaturization, and which ensures a desired capacitance value large enough for stable operation of a semiconductor memory device in spite of miniaturization. The capacitor is comprised of a lower electrode formed over an interlayer dielectric layer of a substrate, an upper electrode, and a dielectric located between the lower and upper electrodes. The lower electrode has a first electrode part and a second electrode part connected to each other. The first electrode part includes a plate-shaped bottom subpart and a sidewall subpart extending upward from the periphery of the bottom subpart. The bottom subpart and the sidewall subpart form an inner space.
    Type: Grant
    Filed: April 17, 2000
    Date of Patent: August 14, 2001
    Assignee: NEC Corporation
    Inventor: Haruo Iwasaki
  • Publication number: 20010007732
    Abstract: The invention relates to a photomask for use in a thermal flow process in which: a photomask is prepared in which a plurality of exposure openings are formed; a resist is applied to the surface of a layer of a semiconductor integrated circuit that is to undergo processing; this resist is patterned by an exposure process through the photomask to form a plurality of openings in the resist that correspond to each of the exposure openings; and the patterned resist is then heated to cause each of the openings to shrink; wherein at least a portion of exposure openings among the plurality of exposure openings are formed in shapes that compensate for anisotropic deformation that occurs in the openings when the patterned resist is heated to cause each of the openings to shrink. Since the openings that are formed in the resist are provided in advance with shapes that compensate for the deformation that occurs when the openings shrink, these openings attain the proper shape after undergoing shrinking and deformation.
    Type: Application
    Filed: January 10, 2001
    Publication date: July 12, 2001
    Applicant: NEC Corporation
    Inventors: Haruo Iwasaki, Shinji Ishida, Tsuyoshi Yoshii
  • Patent number: 6200845
    Abstract: The present invention provides a method of forming at least a bottom electrode of a capacitor in a semiconductor device. The method comprises the steps forming a first insulation film on a multilayer structure over a semiconductor substrate; forming at least a contact hole which penetrates through the first insulation film and the multilayer structure to reach a surface of the semiconductor substrate; selectively removing the first insulation film to form mask patterns on the multilayer structure; forming a single conductive film which extends within the at least contact hole and over the multilayer structure as well as cover the mask patterns; forming a second insulation film on the single conductive film; partially removing the second insulation film and the single conductive film over the mask patterns so that tops of the mask patterns are shown; and removing remaining parts of the second insulation film and the mask patterns to form at least a bottom electrode comprising a single conductive layer.
    Type: Grant
    Filed: April 20, 2000
    Date of Patent: March 13, 2001
    Assignee: NEC Corporation
    Inventor: Haruo Iwasaki
  • Patent number: 6200853
    Abstract: A method of manufacturing a semiconductor device having capacitor contact holes.
    Type: Grant
    Filed: October 7, 1999
    Date of Patent: March 13, 2001
    Assignee: NEC Corporation
    Inventor: Haruo Iwasaki
  • Patent number: 6090523
    Abstract: An antireflection film includes a base resin and an additive resin, the additive resin having a dry etching rate higher than that of the base resin. A photoresist pattern is formed and the antireflection film is selectively etched using the photoresist pattern as a mask. The molecular weight and weight percent of the additive resin are selected to provide an etching rate for the antireflection film that permits selective removal of the antireflection film while leaving an effective amount of the photoresist.
    Type: Grant
    Filed: April 3, 1998
    Date of Patent: July 18, 2000
    Assignee: NEC Corporation
    Inventors: Norihiko Samoto, Haruo Iwasaki, Atsushi Nishizawa, Tsuyoshi Yoshii, Hiroshi Yoshino