Abstract: A data transfer controller is provided which can reduce a CPU control load necessary for data transfer cyclically using a plurality of data transfer areas. A DMAC constituting the data transfer controller is initially set with a transfer start address of a transfer source or transfer destination by a CPU, issues an interrupt to CPU each time the data transfer responding to a transfer request from the transfer source reaches a predetermined data amount based upon the transfer start address, and initializes an address of the transfer source or transfer destination to the transfer start address each time the interrupt is issued predetermined plural times. After CPU sets once the data transfer conditions to DMAC, CPU can continue data processing by repetitively using a limited number of memory areas, without performing any process of repetitively setting the data transfer conditions necessary for a data transfer control for receiving voice data.

Abstract: A signal processing method and system in a receiving apparatus including a receiving equalizer circuit are provided for extracting transmission data from a received signal inputted via a transmission path every transmission frame having a predetermined synchronization pattern and transmission data. A phase error is detected from the received signal extracted in synchronism with a sampling signal in the receiving equalizer circuit. The frequency of the sampling signal is controlled until the phase error becomes minimum. In parallel, it is detected whether the frame synchronization pattern is present in the received signal in a predetermined interval or not. When the presence of the frame synchronization pattern is not detected after the phase has been stabilized by frequency control of the sampling signal, the sampling phase of the received signal is judged to be in the quasi-convergence state. Then the frequency of the sampling signal is forcibly changed largely.