Patents by Inventor Haruo Kawata
Haruo Kawata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11626323Abstract: A semiconductor device is made by: forming a metal film containing Al on a surface of a substrate product including a substrate and a nitride semiconductor layer on the substrate, the metal film covering a via hole forming predetermined region, and the surface of the substrate product being located on the nitride semiconductor layer side, forming an etching mask having an opening for exposing the via hole forming predetermined region on a back surface of the substrate product, the back surface of the substrate product being located on the substrate side, and forming a via hole in the substrate product by reactive ion etching, the via hole reaching the surface from the back surface and exposing the metal film. In the forming of the via hole, a reaction gas containing fluorine is used during a period at least including a termination of etching.Type: GrantFiled: February 16, 2021Date of Patent: April 11, 2023Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventors: Toshiyuki Kosaka, Haruo Kawata
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Publication number: 20210166970Abstract: A semiconductor device is made by: forming a metal film containing Al on a surface of a substrate product including a substrate and a nitride semiconductor layer on the substrate, the metal film covering a via hole forming predetermined region, and the surface of the substrate product being located on the nitride semiconductor layer side, forming an etching mask having an opening for exposing the via hole forming predetermined region on a back surface of the substrate product, the back surface of the substrate product being located on the substrate side, and forming a via hole in the substrate product by reactive ion etching, the via hole reaching the surface from the back surface and exposing the metal film. In the forming of the via hole, a reaction gas containing fluorine is used during a period at least including a termination of etching.Type: ApplicationFiled: February 16, 2021Publication date: June 3, 2021Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventors: Toshiyuki KOSAKA, Haruo KAWATA
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Patent number: 10943821Abstract: A method of manufacturing a semiconductor device includes: forming a metal film containing Al on a surface of a substrate product including a substrate and a nitride semiconductor layer on the substrate, the metal film covering a via hole forming predetermined region, and the surface of the substrate product being located on the nitride semiconductor layer side, forming an etching mask having an opening for exposing the via hole forming predetermined region on a back surface of the substrate product, the back surface of the substrate product being located on the substrate side, and forming a via hole in the substrate product by reactive ion etching, the via hole reaching the surface from the back surface and exposing the metal film. In the forming of the via hole, a reaction gas containing fluorine is used during a period at least including a termination of etching.Type: GrantFiled: July 25, 2019Date of Patent: March 9, 2021Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventors: Toshiyuki Kosaka, Haruo Kawata
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Publication number: 20200035551Abstract: A method of manufacturing a semiconductor device includes: forming a metal film containing Al on a surface of a substrate product including a substrate and a nitride semiconductor layer on the substrate, the metal film covering a via hole forming predetermined region, and the surface of the substrate product being located on the nitride semiconductor layer side, forming an etching mask having an opening for exposing the via hole forming predetermined region on a back surface of the substrate product, the back surface of the substrate product being located on the substrate side, and forming a via hole in the substrate product by reactive ion etching, the via hole reaching the surface from the back surface and exposing the metal film. In the forming of the via hole, a reaction gas containing fluorine is used during a period at least including a termination of etching.Type: ApplicationFiled: July 25, 2019Publication date: January 30, 2020Applicant: Sumitomo Electric Device Innovations, Inc.Inventors: Toshiyuki KOSAKA, Haruo KAWATA
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Patent number: 8476166Abstract: A manufacturing method of a semiconductor device includes: forming step of forming an etching mask on a second main face of a substrate, the etching mask being made of Cu or Cu alloy and having an opening, the second main face being on an opposite side of a first main face of the substrate where a nitride semiconductor layer is provided; a first etching step of applying a dry etching to the second main face of the substrate with use of the etching mask so that all of or a part of the nitride semiconductor layer is left; a removing step of removing the etching mask after the first etching step; and a second etching step of dry-etching the left nitride semiconductor layer after the removing step.Type: GrantFiled: September 29, 2010Date of Patent: July 2, 2013Assignee: Sumitomo Electric Device Innovations, Inc.Inventors: Toshiyuki Kosaka, Haruo Kawata, Tsutomu Komatani
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Publication number: 20110081784Abstract: A manufacturing method of a semiconductor device includes: forming step of forming an etching mask on a second main face of a substrate, the etching mask being made of Cu or Cu alloy and having an opening, the second main face being on an opposite side of a first main face of the substrate where a nitride semiconductor layer is provided; a first etching step of applying a dry etching to the second main face of the substrate with use of the etching mask so that all of or a part of the nitride semiconductor layer is left; a removing step of removing the etching mask after the first etching step; and a second etching step of dry-etching the left nitride semiconductor layer after the removing step.Type: ApplicationFiled: September 29, 2010Publication date: April 7, 2011Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventors: Toshiyuki Kosaka, Haruo Kawata, Tsutomu Komatani
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Patent number: 4791471Abstract: In a semiconductor integrated circuit device, a plurality of a field effect transistors are formed on a (110) crystal surface of a group III-V compound semiconductor substrate having a zinc blend type crystal structure.Type: GrantFiled: February 16, 1988Date of Patent: December 13, 1988Assignee: Fujitsu LimitedInventors: Tsukasa Onodera, Haruo Kawata, Toshiro Futatsugi
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Patent number: 4777517Abstract: An IC device comprising a plurality of FET's using a compound semiconductor, more specifically, a zincblende type semiconductor substrate, having a surface of a (111) plane. By use of this plane, differences of characteristics of the FET's depending on directions along which gates of the FET's are arranged when the gate length is made shorter are prevented, allowing arrangement of gates of the FET's in different directions, particularly perpendicular to each other, with making the gate length shorter to miniaturize and densify the device.Type: GrantFiled: November 26, 1985Date of Patent: October 11, 1988Assignee: Fujitsu LimitedInventors: Tsukasa Onodera, Haruo Kawata, Toshiro Futatsugi
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Patent number: 4642879Abstract: High transconductance is obtained in GaAs FET's by forming a channel layer having a carrier concentration monotonously decreasing from the interface of the channel layer and a control gate toward the interface of the channel layer and the substrate it is formed in. This is established by ion implantation of the channel layer through an insulating layer, preferably an AlN layer, on a GaAs substrate. An AlN layer is preferable since it has no adverse effects on the GaAs substrate during ion implantation and the following heat treatment, allowing higher uniformity of the threshold voltages of the FET's.Type: GrantFiled: November 28, 1983Date of Patent: February 17, 1987Assignee: Fujitsu LimitedInventors: Haruo Kawata, Hidetoshi Nishi