Patents by Inventor Haruo Nishiura

Haruo Nishiura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6114826
    Abstract: In an apparatus for driving a stepping motor in a micro step manner by a PWM control signal generated based on a sense voltage, including a sense resistor for generating the sense voltage, a driving current path including the sense resistor and the stepping motor is provided and is operated so that a driving current flows through the stepping motor, when the PWM control signal is activated. A regenerative current path including the sense resistor and is provided the stepping motor and is operated so that a regenerative current flows through the stepping motor, when the PWM control signal is not activated. A resistance of the regenerative current path is larger than a resistance of the driving current path.
    Type: Grant
    Filed: April 28, 1998
    Date of Patent: September 5, 2000
    Assignee: NEC Corporation
    Inventors: Haruo Nishiura, Fumiyuki Niwa
  • Patent number: 5132993
    Abstract: A shift register circuit includes a logical operator which is added to an output terminal of a latch portion and takes a logical operation of input and output signals of the latch portion and outputs its result as a bit signal. The signal of a bit component is shifted to a higher order bit every half of the period of a clock signal so that a shifting speed thereof can be made two times faster than that in a conventional shift register circuit. It may be arranged such that a higher order bit section starts to output a signal after the preceding lower order bit section outputs a low level signal thereby enabling to avoid the signals outputted by the bit sections neighboring to each other becoming simultaneously intermediate values between a high level and a low level. Also, the bit sections may be cascade-connected such that each of the sections takes a logical operation of the input and output signals of the latch portion. In view of the configuration involved, the number of elements per bit can be reduced.
    Type: Grant
    Filed: December 20, 1990
    Date of Patent: July 21, 1992
    Assignee: NEC Corporation
    Inventors: Haruo Nishiura, Hiroaki Azuhata