Abstract: Grooves are formed on the front surfaces of first and second semiconductor wafers each including an aggregate of a plurality of semiconductor chips. The grooves each extend on a dicing line set between the semiconductor chips and to have a larger width than the dicing line. Thereafter the first and second semiconductor wafers are arranged so that the front surfaces thereof are opposed to each other, and the space between the first semiconductor wafer and the second semiconductor wafer is sealed with underfill. Thereafter the rear surfaces of the first and second semiconductor wafers are polished until at least the grooves are exposed, and a structure including the first and second semiconductor wafers and the underfill is cut on the dicing line.

Abstract: Grooves are formed on the front surfaces of first and second semiconductor wafers each including an aggregate of a plurality of semiconductor chips. The grooves each extend on a dicing line set between the semiconductor chips and to have a larger width than the dicing line. Thereafter the first and second semiconductor wafers are arranged so that the front surfaces thereof are opposed to each other, and the space between the first semiconductor wafer and the second semiconductor wafer is sealed with underfill. Thereafter the rear surfaces of the first and second semiconductor wafers are polished until at least the grooves are exposed, and a structure including the first and second semiconductor wafers and the underfill is cut on the dicing line.

Abstract: Grooves are formed on the front surfaces of first and second semiconductor wafers each including an aggregate of a plurality of semiconductor chips. The grooves each extend on a dicing line set between the semiconductor chips and to have a larger width than the dicing line. Thereafter the first and second semiconductor wafers are arranged so that the front surfaces thereof are opposed to each other, and the space between the first semiconductor wafer and the second semiconductor wafer is sealed with underfill. Thereafter the rear surfaces of the first and second semiconductor wafers are polished until at least the grooves are exposed, and a structure including the first and second semiconductor wafers and the underfill is cut on the dicing line.

Abstract: A method includes the steps of: (a) fixing a front surface of a wafer (semiconductor wafer) having the front surface, a plurality of chip regions formed on the front surface, a dicing region formed between the chip regions, and a rear surface opposite to the front surface to the supporting member; (b) in a state of having the wafer fixed to the supporting member, grinding the rear surface of the wafer to expose the rear surface; (c) in a state of having the wafer fixed to the supporting member, dividing the wafer into the chip regions; (d) etching side surfaces of the chip regions to remove crushed layers formed in the step (c) on the side surfaces and obtain a plurality of semiconductor chips. After the steps (e) and (d), the plurality of divided chip regions are peeled off from the supporting member to obtain a plurality of semiconductor chips.

Abstract: A method includes the steps of: (a) fixing a front surface of a wafer (semiconductor wafer) having the front surface, a plurality of chip regions formed on the front surface, a dicing region formed between the chip regions, and a rear surface opposite to the front surface to the supporting member; (b) in a state of having the wafer fixed to the supporting member, grinding the rear surface of the wafer to expose the rear surface; (c) in a state of having the wafer fixed to the supporting member, dividing the wafer into the chip regions; (d) etching side surfaces of the chip regions to remove crushed layers formed in the step (c) on the side surfaces and obtain a plurality of semiconductor chips. After the steps (e) and (d), the plurality of divided chip regions are peeled off from the supporting member to obtain a plurality of semiconductor chips.

Abstract: Grooves are formed on the front surfaces of first and second semiconductor wafers each including an aggregate of a plurality of semiconductor chips. The grooves each extend on a dicing line set between the semiconductor chips and to have a larger width than the dicing line. Thereafter the first and second semiconductor wafers are arranged so that the front surfaces thereof are opposed to each other, and the space between the first semiconductor wafer and the second semiconductor wafer is sealed with underfill. Thereafter the rear surfaces of the first and second semiconductor wafers are polished until at least the grooves are exposed, and a structure including the first and second semiconductor wafers and the underfill is cut on the dicing line.

Abstract: A semiconductor device of the present invention includes a semiconductor chip with bumps on a surface, and an adhesion sheet on the surface of semiconductor chip. The adhesion sheet has a film base material layer and a film adhesion layer for adhering the film base material layer to the semiconductor chip, and a part of the sheet melts upon heating and tears in response to pressure applied during flip chip bonding. Therefore, it is possible to obtain a semiconductor device which enables good flip chip bonding without any gaps between a device and a substrate in a simple manufacturing process, and to manufacture the semiconductor device.

Abstract: A semiconductor device of the present invention includes a semiconductor chip with bumps formed on its surface, and an adhesion sheet provided on the bumps-formed surface of semiconductor chip. Adhesion sheet has a film base material layer and a film adhesion layer for adhering film base material layer to semiconductor chip, and it has such a structure that a part of the sheet melts by heating and tears by pressuring during flip chip bonding. Therefore, it is possible to obtain a semiconductor device which enables good flip chip bonding without any gaps between a device and a substrate by a simple manufacturing process, and to obtain a method of manufacturing the semiconductor device.

Abstract: A semiconductor package has a die pad, a die mounted on the die pad, a plurality of outer leads electrically connected to electrodes of the die by bonding wires, and a sealing member. The sealing member seals therein the die, the bonding wires, parts of the outer leads and a part of the die pad. Further the sealing member has an upper surface on the side of the die and a lower surface on the side of the die pad. The outer leads have upper connecting surfaces on the side of the upper surface of the sealing member, and lower connecting surfaces on the side of the lower surface of the sealing member. The outer leads have a height from a plane including the lower surface of the sealing member greater than that of the upper surface of the sealing member from the same plane.

Abstract: A pad electrode is formed on a main surface of a semiconductor chip. A passivation film, which covers a surface portion of the pad electrode, is formed on the main surface of the semiconductor chip. An internal connection conductor is formed on a surface portion of the pad electrode. The semiconductor chip is covered with a molding resin which exposes only a top surface of the internal connection conductor. An external connection conductor is formed on a top surface of the internal connection conductor. The external connection conductor has a substantially flat top surface. Thereby, a plastic molded semiconductor package can be easily mounted on a printed board, and can have improved reliability after being joined on the printed board.

Abstract: A pad electrode is formed on a main surface of a semiconductor chip. A passivation film, which covers a surface portion of the pad electrode, is formed on the main surface of the semiconductor chip. An internal connection conductor is formed on a surface portion of the pad electrode. The semiconductor chip is covered with a molding resin which exposes only a top surface of the internal connection conductor. An external connection conductor is formed on a top surface of the internal connection conductor. The external connection conductor has a substantially flat top surface. Thereby, a plastic molded semiconductor package can be easily mounted on a printed board, and can have improved reliability after being joined on the printed board.

Abstract: A pad electrode is formed on a main surface of a semiconductor chip. A passivation film, which covers a surface portion of the pad electrode, is formed on the main surface of the semiconductor chip. An internal connection conductor is formed on a surface portion of the pad electrode. The semiconductor chip is covered with a molding resin which exposes only a top surface of the internal connection conductor. An external connection conductor is formed on a top surface of the internal connection conductor. The external connection conductor has a substantially flat top surface. Thereby, a plastic molded semiconductor package can be easily mounted on a printed board, and can have improved reliability after being joined on the printed board.

Abstract: A pad electrode is formed on a main surface of a semiconductor chip. A passivation film, which covers a surface portion of the pad electrode, is formed on the main surface of the semiconductor chip. An internal connection conductor is formed on a surface portion of the pad electrode. The semiconductor chip is covered with a molding resin which exposes only a top surface of the internal connection conductor. An external connection conductor is formed on a top surface of the internal connection conductor. The external connection conductor has a substantially flat top surface. Thereby, a plastic molded semiconductor package can be easily mounted on a printed board, and can have improved reliability after being joined on the printed board.

Abstract: The present invention provides a semiconductor integrated circuit apparatus with a heat sink that can be changed in size, that accommodates a board and electronic parts having different sizes, and that increases heat radiation. The present invention includes a cooling member facing and connected to electronic parts via a thermally conductive resin or thermally conductive fat and fatty oil and at least two thermally conductive clamps that are soldered to a board and that support portions of the perimeter of the cooling member.

Abstract: A semiconductor device includes a molded resin encapsulating a semiconductor chip, outer leads extending from the molded resin and having free ends, and a resin layer connecting and supporting the outer leads along the entire length of the outer leads. The resin layer may have an activating ability for soldering. A method for manufacturing a semiconductor device includes preparing a semiconductor device having a molded resin and a plurality of outer lead portions extending from the molded resin and connected to a lead frame, forming a resin film on and between the outer lead portions; cutting the lead portions to provide cantilevered outer leads having free ends; lead-forming the outer leads with lead-forming dies while heating the resin film to form a resin layer connecting and supporting the outer leads along the entire lengths of the outer leads, and taking the semiconductor device out of the lead-forming dies after the resin layer has been cured.

Abstract: A laser OLB apparatus includes an XY table; a bonding laser source for irradiating bonding parts between bonding lands of a substrate and leads of a semiconductor device located on the substrate thereby bonding the bonding parts; a recognition device for recognizing whether the leads of the semiconductor device are free of flexure and deviation; and a control unit for controlling the XY table and the laser source so that bonding is conducted only when the recognition device has recognized that the leads are free of flexure and deviation.

Abstract: A semiconductor device according to the present invention has reduced inductance on a power supply line, a grounding line, and signal lines. In this invention, to reduce the length of the power supply connection and that of the grounding connection, a power supply metal post and a grounding metal post are respectively provided on a power supply lead of a semiconductor chip and grounding lead of the semiconductor chip perpendicular to the leads. The metal posts protrude from the resin encapsulating the chip and are connected to lands or a conductive circuit pattern on a printed circuit board. Furthermore, a planar conductor commonly connecting the power supply or grounding potentials is provided.

Abstract: A semiconductor device includes an insulating substrate; a semiconductor chip on which plural electrodes including at least one ground electrode and at least one power source electrode are disposed; plural leads supported by an obverse surface of the insulating substrate, the plural leads being connected to corresponding electrodes on the semiconductor chip; at least one grounding conductor plate on a reverse surface of the insulating substrate; and at least one power source conductor plate on the reverse surface of the insulating substrate.

Abstract: A manufacturing method for a semiconductor device in which an electrode of a semiconductor chip is electrically connected to an inner lead of a carrier tape. The electrodes of the semiconductor chip are brought into contact with the inner lead of the carrier tape. Bonding is performed with inner lead droop controlled to no more than 80 .mu.m.

Abstract: A packaged semiconductor device includes an insulating film having an opening, a semiconductor chip disposed in the opening of the insulating film and having a plurality of electrodes, a plurality of leads, each having one end connected to a corresponding electrode, the plurality of leads being supported on the insulating film, a heat radiator disposed opposite and spaced from the semiconductor chip, and a resin package body encapsulating the semiconductor chip and part of the heat radiator, leaving a surface of the heat radiator externally exposed and the second ends of the plurality of leads extending outwardly from the package.