Patents by Inventor Haruo Shoji

Haruo Shoji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060259729
    Abstract: The present invention aims at providing a semiconductor memory device that can be operational in a desired boot block mode, regardless of the original boot block type of the device, by facilitating rewriting of the memory device. A sector address from an outside source is inputted into a sector-address conversion circuit, which converts the sector address into an internal address, and a memory cell array is accessed through an address decoder circuit. Suppose that each of banks of the memory device is configured as a bottom boot type. By converting the sector address by the sector-address conversion circuit such that the sector-address now appears to the outside in the reverse order, each of the banks now functions as a top boot type.
    Type: Application
    Filed: July 17, 2006
    Publication date: November 16, 2006
    Inventor: Haruo Shoji
  • Patent number: 7114052
    Abstract: The present invention aims at providing a semiconductor memory device that can be operational in a desired boot block mode, regardless of the original boot block type of the device, by facilitating rewriting of the memory device. A sector address from an outside source is inputted into a sector-address conversion circuit, which converts the sector address into an internal address, and a memory cell array is accessed through an address decoder circuit. Suppose that each of banks of the memory device is configured as a bottom boot type. By converting the sector address by the sector-address conversion circuit such that the sector-address now appears to the outside in the reverse order, each of the banks now functions as a top boot type.
    Type: Grant
    Filed: January 17, 2002
    Date of Patent: September 26, 2006
    Assignee: Fujitsu Limited
    Inventor: Haruo Shoji
  • Patent number: 6862672
    Abstract: A plurality of memory cells corresponding to an address space larger than 2n and smaller than 2(n+1), an invalid address detecting circuit, and an invalid signal outputting circuit are comprised. Upon command input, the invalid address detecting circuit invalidates a command in the case where the invalid address detecting circuit detects a fact that an address signal supplied from exterior indicates an invalid address space. Therefore, at the time of invalid address supply, internal circuits are not activated and an erroneous write or erase operation can be prevented. Since the internal circuits do not operate, power consumption can be reduced substantially. The invalid signal outputting circuit outputs an invalid signal by receiving the fact of invalid address signal detection by the invalid address detecting circuit. Therefore, a system unit mounting the semiconductor memory device can easily recognize that the invalid address signal has been supplied to the semiconductor memory device.
    Type: Grant
    Filed: May 31, 2000
    Date of Patent: March 1, 2005
    Assignee: Fujitsu Limited
    Inventors: Tomomi Furudate, Takaaki Ichikawa, Junya Kawamata, Hideyuki Furukawa, Haruo Shoji, Yuzuru Matsuno, Tatsuya Yoshimoto, Masato Kitamura
  • Publication number: 20020099920
    Abstract: The present invention aims at providing a semiconductor memory device that can be operational in a desired boot block mode, regardless of the original boot block type of the device, by facilitating rewriting of the memory device. A sector address from an outside source is inputted into a sector-address conversion circuit, which converts the sector address into an internal address, and a memory cell array is accessed through an address decoder circuit. Suppose that each of banks of the memory device is configured as a bottom boot type. By converting the sector address by the sector-address conversion circuit such that the sector-address now appears to the outside in the reverse order, each of the banks now functions as a top boot type.
    Type: Application
    Filed: January 17, 2002
    Publication date: July 25, 2002
    Applicant: FUJITSU LIMITED
    Inventor: Haruo Shoji
  • Patent number: 6215717
    Abstract: A semiconductor memory device which can reduce a time required for a write-protection setting operation when a plurality of blocks are to be write-protected. A write area of the semiconductor memory device is divided into a predetermined number of blocks each of which is rewritable on an individual block basis. Write-protection information is simultaneously provided to a plurality of blocks that are arbitrarily designated from among the predetermined number of blocks so that the plurality of blocks are simultaneously subjected to the write-protection setting operation.
    Type: Grant
    Filed: September 28, 1998
    Date of Patent: April 10, 2001
    Assignee: Fujitsu Limited
    Inventors: Tetsuji Takeguchi, Haruo Shoji