Abstract: A backing member includes: a resin layer which contains a filler; and a plurality of leads each of which is embedded in the resin layer to penetrate through the resin layer from an upper surface of the resin layer to a lower surface of the resin layer. Each of the leads includes a wiring portion, and a terminal portion connected to one end of the wiring portion. A width dimension and a depth dimension of the wiring portion are smaller than a width dimension and a depth dimension of the terminal portion, and an interval between adjacent ones of the wiring portions of the leads is wider than an average particle size of the filler.

Abstract: A wiring component electrically connects a first semiconductor element, including first and second electrode terminals, and a second semiconductor element, including third and fourth electrode terminals. The wiring component includes first and second connection terminals respectively connected to the first and third electrode terminals. A third connection terminal is connected to the second electrode terminal, and a fourth connection terminal is connected to the fourth electrode terminal. An insulation layer embeds the wiring component and the third and fourth connection terminals. A wiring layer is formed on a lower surface of the insulation layer and connected to an internal connection terminal and the third and fourth external terminals. Upper surfaces of the first to fourth external terminals are located coplanar with one another.

Abstract: A wiring component electrically connects a first semiconductor element, including first and second electrode terminals, and a second semiconductor element, including third and fourth electrode terminals. The wiring component includes first and second connection terminals respectively connected to the first and third electrode terminals. A third connection terminal is connected to the second electrode terminal, and a fourth connection terminal is connected to the fourth electrode terminal. An insulation layer embeds the wiring component and the third and fourth connection terminals. A wiring layer is formed on a lower surface of the insulation layer and connected to an internal connection terminal and the third and fourth external terminals. Upper surfaces of the first to fourth external terminals are located coplanar with one another.

Abstract: A backing member includes: a resin layer which contains a filler; and a plurality of leads each of which is embedded in the resin layer to penetrate through the resin layer from an upper surface of the resin layer to a lower surface of the resin layer. Each of the leads includes a wiring portion, and a terminal portion connected to one end of the wiring portion. A width dimension and a depth dimension of the wiring portion are smaller than a width dimension and a depth dimension of the terminal portion, and an interval between adjacent ones of the wiring portions of the leads is wider than an average particle size of the filler.

Abstract: An electronic component device includes a first insulating layer, a wiring layer, a second insulating layer, a wiring component, and first and second electronic components. The first insulating layer includes a mounting region on an upper surface thereof. The wiring layer is formed on the first insulating layer except the mounting region. The second insulating layer is formed on the first insulating layer, is formed with an opening in the mounting region, and is formed with first and second connection holes on the wiring layer. The wiring component is mounted in the mounting region and in the opening and includes first and second connecting portions. The first electronic component is connected to the first connecting portion and is connected to the wiring layer in the first connection hole. The second electronic component is connected to the second connecting portion and is connected to the wiring layer in second connection hole.

Abstract: A semiconductor device includes a wiring substrate, a semiconductor chip whose connection terminal is connected to the wiring substrate, an underfill resin formed from a clearance between the wiring substrate and the semiconductor chip to a periphery area of the semiconductor chip, wherein the underfill resin in the periphery area is formed at a same height as an upper surface of the semiconductor chip, an auxiliary member fixed on the semiconductor chip by an adhesive layer, and including a protruding portion which protrudes to an outside from the semiconductor chip, and the protruding portion arranged at least on the underfill resin via the adhesive layer, and a sealing resin sealing the underfill resin and at least side faces of the auxiliary member, wherein respective coefficients of thermal expansion of the auxiliary member and the adhesive layer are larger than a coefficient of thermal expansion of the semiconductor chip.

Abstract: A semiconductor device includes a wiring substrate, a semiconductor chip whose connection terminal is connected to the wiring substrate, an underfill resin formed from a clearance between the wiring substrate and the semiconductor chip to a periphery area of the semiconductor chip, wherein the underfill resin in the periphery area is formed at a same height as an upper surface of the semiconductor chip, an auxiliary member fixed on the semiconductor chip by an adhesive layer, and including a protruding portion which protrudes to an outside from the semiconductor chip, and the protruding portion arranged at least on the underfill resin via the adhesive layer, and a sealing resin sealing the underfill resin and at least side faces of the auxiliary member, wherein respective coefficients of thermal expansion of the auxiliary member and the adhesive layer are larger than a coefficient of thermal expansion of the semiconductor chip.

Abstract: An electronic component is provided between at least two wiring boards. An electrode of the electronic component is electrically connected to at least one of the wiring boards. Also, the wiring boards and are electrically connected to each other. Additionally, the gap between the wiring boards and is sealed with a resin. The electronic component built-in substrate is featured in that a bonding pad formed on one of the wiring boards and is electrically connected to an electrode of the electronic component by a bonding wire, and that at least a connection portion between the electrode of the electronic component and the bonding wire is coated with a protection material.

Abstract: It is an electronic component built-in substrate 100 configured as follows. That is, an electronic component 30 is provided between at least two wiring boards 10 and 20. An electrode 34 of the electronic component 30 is electrically connected to at least one of the wiring boards. Also, the wiring boards 10 and 20 are electrically connected to each other. Additionally, the gap between the wiring boards 10 and 20 is sealed with a resin. The electronic component built-in substrate 100 is featured in that a bonding pad 12 formed on one of the wiring boards 10 and 20 is electrically connected to an electrode 32 of the electronic component 30 by a bonding wire 60, and that at least a connection portion between the electrode 32 of the electronic component 30 and the bonding wire 60 is coated with a protection material 70.

Abstract: A semiconductor device characterized in that connection pads for wire bonding are arranged at peripheral regions of an electrode terminal formation surface of a semiconductor chip, test pads for testing the semiconductor chip are arranged in an inside region surrounded by said peripheral regions of said electrode terminal formation surface, and a plurality of rewiring patterns extend from the peripheral regions to said inside region of said electrode terminal formation surface and the individual rewiring patterns connect the individual electrode terminals and the corresponding connection pads and test pads.

Abstract: A mounting board on which a semiconductor chip having multiple connection bumps is to be mounted by flip-chip bonding is disclosed. The mounting board includes multiple connection pads to be electrically connected to the corresponding connection bumps, where the connection pads have respective surfaces coated with solder; and an insulating layer configured to surround the connection pads and isolate the connection pads from each other. Each of the connection pads has a first region and at least one second region to be connected to a corresponding one of the connection bumps. The first region has a surface substantially as high as a surface of the insulating layer and the second region has a surface lower than the surface of the first region.

Abstract: A semiconductor device characterized in that connection pads for wire bonding are arranged at peripheral regions of an electrode terminal formation surface of a semiconductor chip, test pads for testing the semiconductor chip are arranged in an inside region surrounded by said peripheral regions of said electrode terminal formation surface, and a plurality of rewiring patterns extend from the peripheral regions to said inside region of said electrode terminal formation surface and the individual rewiring patterns connect the individual electrode terminals and the corresponding connection pads and test pads.

Abstract: A method of production of a semiconductor device able to utilize a conventional production system for a resin board to thereby produce a wafer level package without increasing the production cost, comprising electrolessly plating the electrode terminals to cover the surfaces of the electrode terminals by a protective film protecting the electrode terminals from laser beams; grinding the back side of the semiconductor wafer to reduce the thickness of the semiconductor wafer before or after forming the protective film; covering the entirety of the electrode terminal forming surface and back side of the semiconductor wafer, having the electrode terminals covered by a protective film and processed to reduce the thickness of the semiconductor wafer, by a resin to form a laminate; and focusing a laser beam toward the electrode terminal forming surface of the semiconductor wafer from outside the laminate to form via holes with the protective film exposed at their bottom surfaces, then filling the via holes by electr

Abstract: A method of production of a semiconductor device able to utilize a conventional production system for a resin board to thereby produce a wafer level package without increasing the production cost, comprising electrolessly plating the electrode terminals to cover the surfaces of the electrode terminals by a protective film protecting the electrode terminals from laser beams; grinding the back side of the semiconductor wafer to reduce the thickness of the semiconductor wafer before or after forming the protective film; covering the entirety of the electrode terminal forming surface and back side of the semiconductor wafer, having the electrode terminals covered by a protective film and processed to reduce the thickness of the semiconductor wafer, by a resin to form a laminate; and focusing a laser beam toward the electrode terminal forming surface of the semiconductor wafer from outside the laminate to form via holes with the protective film exposed at their bottom surfaces, then filling the via holes by electr

Abstract: A mounting substrate on which a semiconductor element is to be mounted by flip-chip bonding, the semiconductor element having a surface on which a plurality of electrode terminals are arranged in a line, each of said electrode terminals having a protruded electrode formed thereon, wherein the surface of the mounting substrate on which the semiconductor element is to be mounted is provided with a protective film having an opening corresponding to an area of the semiconductor element where the protruded electrodes are located, a plurality of connection electrodes being arranged in the opening, the connection electrodes being provided with a solder for bonding it to the protruded electrodes, and being arranged at the same interval as that of the protruded electrodes, and each of the connection electrodes being connected to a wiring pattern of the mounting substrate, and wherein the length of a portion of the connection electrode from the center of the opening to the end thereof that is not connected with the wir

Abstract: A mounting substrate on which a semiconductor element is to be mounted by flip-chip bonding, the semiconductor element having a surface on which a plurality of electrode terminals are arranged in a line, each of said electrode terminals having a protruded electrode formed thereon, wherein the surface of the mounting substrate on which the semiconductor element is to be mounted is provided with a protective film having an opening corresponding to an area of the semiconductor element where the protruded electrodes are located, a plurality of connection electrodes being arranged in the opening, the connection electrodes being provided with a solder for bonding it to the protruded electrodes, and being arranged at the same interval as that of the protruded electrodes, and each of the connection electrodes being connected to a wiring pattern of the mounting substrate, and wherein the length of a portion of the connection electrode from the center of the opening to the end thereof that is not connected with the wir

Abstract: A multi-chip module includes a substrate, an interconnection pattern provided on the substrate, a plurality of semiconductor chips provided commonly upon the substrate in electrical connection with the interconnection pattern, a plurality of thermally conductive blocks each provided on corresponding one of the plurality of semiconductor chips in an intimate contact therewith, a resin package body that encapsulates the plurality of semiconductor chips and the plurality of thermally conductive blocks together with the substrate, such that the resin package body has an upper major surface substantially flush with the upper major surfaces of the plurality of thermally conductive blocks, and a heat sink mounted upon the upper major surface of the resin package body such that the heat sink establishes an intimate contact with respective upper major surfaces of the thermally conducting blocks.

Abstract: A multi-chip module (MCM) having semiconductor chips on a top surface of multi-layered interconnection circuits formed on a planar surface of a substrate including: (a) multi-layered interconnection circuits comprising alternatively laminated interconnection layers with insulating layers, and thermal contacts, each of the thermal contacts comprising successively laminated interconnection layers on a bottom and on side-walls of a vertical hole penetrating a plurality of the insulating layers, and a thermal conductor filling the vertical hole on the successively laminated interconnection layers, and (b) a plurality of the semiconductor chips attached to the thermal conductor.

Abstract: A thermal recording head comprising an insulating substrate which has thereon a heat generating resistor pattern made of a thin-film resistor, an electrode pattern having a common power supply electrode pattern portion and a common grounded electrode pattern portion, for supplying the power to the resistor pattern, and a controlling electrode pattern portion, and switching elements for controlling the supply of the power to the resistor pattern. The electrode pattern is made of a thick-film copper paste by a printing process. The operation of the switching elements is controlled by the controlling electrode pattern portion.Also disclosed is a process for manufacturing a wiring substrate for a thermal recording head.

Abstract: Cracks in an Ta.sub.2 O.sub.5 anti-abrasion layer of a thermal printing head resulting from the crystallization of the Ta.sub.2 O.sub.5 in the layer, are suppressed by the addition of SiO.sub.2 to the layer. The anti-abrasion layer is provided as a uniform mixture of Ta.sub.2 O.sub.5 and SiO.sub.2 throughout the layer by sputtering a target composed of a mixture containing tantalum and silicon ingredients onto an antioxidation layer. The thermal printing head is also subjected to annealing to stabilize the resistivity of the heating elements.