Patents by Inventor Haruo Sudo
Haruo Sudo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230243062Abstract: A silicon wafer is provided which is a Czochralski wafer formed of silicon, and a method for producing the silicon wafer are provided. The wafer includes a bulk layer having an oxygen concentration of 0.5×1018/cm3 or more; and a surface layer extending from the surface of the wafer to 300 nm in depth, and having an oxygen concentration of 2×1018/cm3 or more.Type: ApplicationFiled: June 14, 2021Publication date: August 3, 2023Inventors: Haruo SUDO, Takashi ISHIKAWA, Koji IZUNOME, Hisashi MATSUMURA, Tatsuhiko AOKI, Shoji IKEDA, Tetsuo ENDOH, Etsuo FUKUDA
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Publication number: 20230073641Abstract: Provided is a method for manufacturing a semiconductor silicon wafer capable of inhibiting P-aggregation defects (Si-P defects) and SF in an epitaxial layer. The method includes a step of forming a silicon oxide film with a thickness of at least 300 nm or thicker only on the backside of the silicon wafer substrate by the CVD method at a temperature of 500° C. or lower after the step of forming the silicon oxide film, a step of heat treatment where the substrate is kept in an oxidizing atmosphere at a constant temperature of 1100° C. or higher and 1250° C. or lower for 30 minutes or longer and 120 minutes or shorter after the heat treatment, a step of removing surface oxide film formed on the front surface of the substrate, and a step of depositing a silicon monocrystalline epitaxial layer on the substrate after the step of removing the surface oxide film.Type: ApplicationFiled: February 16, 2021Publication date: March 9, 2023Applicant: GLOBALWAFERS JAPAN CO., LTD.Inventors: Takeshi SENDA, Haruo SUDO
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Patent number: 11162191Abstract: A processing temperature TS by a rapid thermal processing furnace is 1250° C. or more and 1350° C. or less, and a cooling rate Rd from the processing temperature is in a range of 20° C./s or more and 150° C./s or less, and thermal processing is performed by adjusting the processing temperature TS and the cooling rate Rd within a range between the upper limit P=0.00207TS·Rd?2.52Rd+13.3 (Formula (A)) and the lower limit P=0.000548TS·Rd?0.605Rd?0.511 (Formula (B)) of an oxygen partial pressure P in a thermal processing atmosphere.Type: GrantFiled: March 23, 2017Date of Patent: November 2, 2021Assignee: GLOBALWAFERS JAPAN CO., LTD.Inventors: Susumu Maeda, Hironori Banba, Haruo Sudo, Hideyuki Okamura, Koji Araki, Koji Sueoka, Kozo Nakamura
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Patent number: 11060983Abstract: An evaluation method of a silicon wafer allows non-destructive and non-contact inspection of a slip that affects the electrical properties of semiconductor devices, without being subjected to restrictions of the surface condition of silicon wafers or processing contents as much as possible. The evaluation method of a silicon wafer includes a step of section analysis where a surface of a single crystal silicon wafer after thermal processing is divided by equally-spaced lines into sections with an area of 1 mm2 or more and 25 mm2 or less and the existence of strain in each of the sections is determined based on a depolarization value of polarized infrared light, and a screening step where the wafer is evaluated as non-defective when the number of adjacent sections being determined to have strain by the section analysis step does not exceed a predetermined threshold value.Type: GrantFiled: July 23, 2018Date of Patent: July 13, 2021Assignee: GLOBALWAFERS JAPAN CO., LTD.Inventors: Haruo Sudo, Nobue Araki, Kazuki Okabe, Koji Araki
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Publication number: 20210055232Abstract: An evaluation method of a silicon wafer allows non-destructive and non-contact inspection of a slip that affects the electrical properties of semiconductor devices, without being subjected to restrictions of the surface condition of silicon wafers or processing contents as much as possible. The evaluation method of a silicon wafer includes a step of section analysis where a surface of a single crystal silicon wafer after thermal processing is divided by equally-spaced lines into sections with an area of 1 mm2 or more and 25 mm2 or less and the existence of strain in each of the sections is determined based on a depolarization value of polarized infrared light, and a screening step where the wafer is evaluated as non-defective when the number of adjacent sections being determined to have strain by the section analysis step does not exceed a predetermined threshold value.Type: ApplicationFiled: July 23, 2018Publication date: February 25, 2021Applicant: GlobalWafers Japan Co., Ltd.Inventors: Haruo SUDO, Nobue ARAKI, Kazuki OKABE, Koji ARAKI
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Publication number: 20200181802Abstract: A processing temperature TS by a rapid thermal processing furnace is 1250° C. or more and 1350° C. or less, and a cooling rate Rd from the processing temperature is in a range of 20° C./s or more and 150° C./s or less, and thermal processing is performed by adjusting the processing temperature TS and the cooling rate Rd within a range between the upper limit P=0.00207TS·Rd?2.52Rd+13.3 (Formula (A)) and the lower limit P=0.000548TS·Rd?0.605Rd?0.511 (Formula (B)) of an oxygen partial pressure P in a thermal processing atmosphere.Type: ApplicationFiled: March 23, 2017Publication date: June 11, 2020Inventors: Susumu MAEDA, Hironori BANBA, Haruo SUDO, Hideyuki OKAMURA, Koji ARAKI, Koji SUEOKA, Kozo NAKAMURA
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Patent number: 10648101Abstract: A silicon wafer includes a denuded zone which is a surface layer and of which the density of vacancy-oxygen complexes which are complexes of vacancies and oxygen is less than 1.0×1012/cm3. An intermediate layer is disposed inwardly of the denuded zone so as to be adjacent to the denuded zone. The density of the vacancy-oxygen complexes in the intermediate layer increases gradually inwardly in the depth direction from the boundary with the denuded zone within a range of 1.0×1012/cm3 or over and less than 5.0×1012/cm3. The intermediate layer has a depth determined corresponding to the depth of the denuded zone. A bulk layer is disposed inwardly of the intermediate layer so as to be adjacent to the intermediate layer. The density of the vacancy-oxygen complexes in the bulk layer is 5.0×1012/cm3 or over.Type: GrantFiled: February 24, 2017Date of Patent: May 12, 2020Assignee: GLOBALWAFERS JAPAN CO., LTD.Inventors: Susumu Maeda, Hironori Banba, Haruo Sudo, Hideyuki Okamura, Koji Araki, Koji Sueoka, Kozo Nakamura
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Publication number: 20190119828Abstract: A silicon wafer includes a denuded zone which is a surface layer and of which the density of vacancy-oxygen complexes which are complexes of vacancies and oxygen is less than 1.0×1012/cm3. An intermediate layer is disposed inwardly of the denuded zone so as to be adjacent to the denuded zone. The density of the vacancy-oxygen complexes in the intermediate layer increases gradually inwardly in the depth direction from the boundary with the denuded zone within a range of 1.0×1012/cm3 or over and less than 5.0×1012/cm3. The intermediate layer has a depth determined corresponding to the depth of the denuded zone. A bulk layer is disposed inwardly of the intermediate layer so as to be adjacent to the intermediate layer. The density of the vacancy-oxygen complexes in the bulk layer is 5.0×1012/cm3 or over.Type: ApplicationFiled: February 24, 2017Publication date: April 25, 2019Inventors: Susumu MAEDA, Hironori BANBA, Haruo SUDO, Hideyuki OKAMURA, Koji ARAKI, Koji SUEOKA, Kozo NAKAMURA
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Patent number: 10141180Abstract: A silicon wafer is manufactured by subjecting a silicon wafer sliced from a silicon single-crystal ingot grown by the Czochralski process to a rapid thermal process in which the silicon wafer is heated to a maximum temperature within a range of 1300 to 1380° C., and kept at the maximum temperature for 5 to 60 seconds; and removing a surface layer of the wafer where a semiconductor device is to be manufactured by a thickness of not less X [?m] which is calculated according to the below equations (1) to (3): X [?m]=a [?m]+b [?m]??(1); a [?m]=(0.0031×(said maximum temperature) [° C.]?3.1)×6.4×(cooling rate)?0.4 [° C./second]??(2); and b [?m]=a/(solid solubility limit of oxygen) [atoms/cm3]/(oxygen concentration in substrate) [atoms/cm3]??(3).Type: GrantFiled: July 31, 2014Date of Patent: November 27, 2018Assignee: GLOBALWAFERS JAPAN CO., LTD.Inventors: Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Takeshi Senda
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Publication number: 20160293446Abstract: Provided is a method for manufacturing a silicon wafer including a first step of heat-treating a raw silicon wafer sliced from a silicon single crystal ingot grown by the Czochralski method in an oxidizing gas atmosphere at a maximum target temperature of 1300 to 1380° C., a second step of removing an oxide film on a surface of the heated-treated silicon wafer obtained in the first step, and a third step of heat-treating the stripped silicon wafer obtained in the second step in a non-oxidizing gas atmosphere at a maximum target temperature of 1200 to 1380° C. and at a heating rate of 1° C./sec to 150° C./sec in order that the silicon wafer may have a maximum oxygen concentration of 1.3×1018 atoms/cm3 or below in a region from the surface up to 7 ?m in depth.Type: ApplicationFiled: March 28, 2016Publication date: October 6, 2016Applicant: GlobalWafers Japan Co., Ltd.Inventors: Haruo SUDO, Koji ARAKI, Tatsuhiko AOKI, Susumu MAEDA
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Patent number: 8999864Abstract: A silicon wafer for preventing a void defect in a bulk region from becoming source of contamination and slip generation in a device process is provided. And a heat-treating method thereof for reducing crystal defects such as COP in a region near the wafer surface to be a device active region is provided. The silicon wafer has a surface region 1 which is a defect-free region and a bulk region 2 including void defect of a polyhedron whose basic shape is an octahedron in which a corner portion of the polyhedron is in the curved shape and an inner-wall oxide film the void defect is removed. The silicon wafer is provided by performing a heat-treating method in which gas to be supplied, inner pressure of spaces and a maximum achievable temperature are set to a predetermined value when subjecting the silicon wafer produced by a CZ method to RTP.Type: GrantFiled: May 28, 2010Date of Patent: April 7, 2015Assignee: Global Wafers Japan Co., Ltd.Inventors: Takeshi Senda, Hiromichi Isogai, Eiji Toyoda, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Koji Izunome, Susumu Maeda, Kazuhiko Kashima, Hiroyuki Saito
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Publication number: 20150044422Abstract: A silicon wafer is manufactured by subjecting a silicon wafer sliced from a silicon single-crystal ingot grown by the Czochralski process to a rapid thermal process in which the silicon wafer is heated to a maximum temperature within a range of 1300 to 1380° C., and kept at the maximum temperature for 5 to 60 seconds; and removing a surface layer of the wafer where a semiconductor device is to be manufactured by a thickness of not less X [?m] which is calculated according to the below equations (1) to (3): X[?m]=a[?m]+b[?m]??(1); a[?m]=(0.0031×(said maximum temperature)[° C.]?3.1)×6.4×(cooling rate)?0.4[° C./second] . . . (2); and b[?m]=a/(solid solubility limit of oxygen) [atoms/cm3]/(oxygen concentration in substrate) [atoms/cm3]??(3).Type: ApplicationFiled: July 31, 2014Publication date: February 12, 2015Inventors: Koji ARAKI, Tatsuhiko AOKI, Haruo SUDO, Takeshi SENDA
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Patent number: 8476149Abstract: A silicon wafer produced from a silicon single crystal ingot grown by Czochralski process is subjected to rapid heating/cooling thermal process at a maximum temperature (T1) of 1300° C. or more, but less than 1380° C. in an oxidizing gas atmosphere having an oxygen partial pressure of 20% or more, but less than 100%. The silicon wafer according to the invention has, in a defect-free region (DZ layer) including at least a device active region of the silicon wafer, a high oxygen concentration region having a concentration of oxygen solid solution of 0.7×1018 atoms/cm3 or more and at the same time, the defect-free region contains interstitial silicon in supersaturated state.Type: GrantFiled: July 30, 2009Date of Patent: July 2, 2013Assignee: Global Wafers Japan Co., Ltd.Inventors: Hiromichi Isogai, Takeshi Senda, Eiji Toyoda, Kumiko Murayama, Koji Izunome, Susumu Maeda, Kazuhiko Kashima, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Yoichiro Mochizuki, Akihiko Kobayashi, Senlin Fu
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Publication number: 20130078588Abstract: A method for heat-treating a silicon wafer is provided in which in-plane uniformity in BMD density along a diameter of a bulk of the wafer grown by the CZ process can be improved. Further, a method for heat-treating a silicon wafer is provided in which in-plane uniformity in BMD size can also be improved and COP of a surface layer of the wafer can be reduced. The method includes a step of a first heat treatment in which the CZ silicon wafer is heated to a temperature from 1325 to 1400° C. in an oxidizing gas atmosphere, held at the temperature, and then cooled at a cooling rate of from 50 to 250° C./second, and a step of a second heat treatment in which the wafer is heated to a temperature from 900 to 1200° C. in a non-oxidizing gas atmosphere, held at the temperature, and then cooled.Type: ApplicationFiled: September 25, 2012Publication date: March 28, 2013Applicant: Covalent Silicon CorporationInventors: Takeshi Senda, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Susumu Maeda
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Patent number: 8399341Abstract: The invention is to provide a method for heat treating a silicon wafer reducing grown-in defects while suppressing generation of slip during RTP and improving surface roughness of the wafer. The method performing a first heat treatment while introducing a rare gas, the first heat treatment comprising the steps of rapidly heating the wafer to T1 of 1300° C. or higher and the melting point of silicon or lower, keeping the wafer at T1, rapidly cooling the wafer to T2 of 400-800° C. and keeping the wafer at T2; and performing a second heat treatment while introducing an oxygen gas in an amount of 20-100 vol. %, the second heat treatment comprising the steps of keeping the wafer at T2, rapidly heating the wafer from T2 to T3 of 1250° C. or higher and the melting point of silicon or lower, keeping the wafer at T3 and rapidly cooling the wafer.Type: GrantFiled: May 17, 2010Date of Patent: March 19, 2013Assignee: Covalent Materials CorporationInventors: Takeshi Senda, Hiromichi Isogai, Eiji Toyoda, Kumiko Murayama, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Koji Izunome, Susumu Maeda, Kazuhiko Kashima
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Patent number: 8252700Abstract: In a method of heat treating a wafer obtained by slicing a silicon single crystal ingot manufactured by the Czochralski method, a rapid heating/cooling heat treatment is carried out by setting a holding time at an ultimate temperature of 1200° C. or more and a melting point of silicon or less to be equal to or longer than one second and to be equal to or shorter than 60 seconds in a mixed gas atmosphere containing oxygen having an oxygen partial pressure of 1.0% or more and 20% or less and argon, and an oxide film having a thickness of 9.1 nm or less or 24.3 nm or more is thus formed on a surface of the silicon wafer.Type: GrantFiled: January 21, 2010Date of Patent: August 28, 2012Assignee: Covalent Materials CorporationInventors: Takeshi Senda, Hiromichi Isogai, Eiji Toyoda, Kumiko Murayama, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Koji Izunome, Susumu Maeda, Kazuhiko Kashima
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Publication number: 20120184091Abstract: The invention is to provide a method for heat treating a silicon wafer reducing grown-in defects while suppressing generation of slip during RTP and improving surface roughness of the wafer. The method performing a first heat treatment while introducing a rare gas, the first heat treatment comprising the steps of rapidly heating the wafer to T1 of 1300° C. or higher and the melting point of silicon or lower, keeping the wafer at T1, rapidly cooling the wafer to T2 of 400-800° C. and keeping the wafer at T2; and performing a second heat treatment while introducing an oxygen gas in an amount of 20-100 vol. %, the second heat treatment comprising the steps of keeping the wafer at T2, rapidly heating the wafer from T2 to T3 of 1250° C. or higher and the melting point of silicon or lower, keeping the wafer at T3 and rapidly cooling the wafer.Type: ApplicationFiled: May 17, 2010Publication date: July 19, 2012Applicant: Covalent Materials CorporationInventors: Takeshi Senda, Hiromichi Isogai, Eiji Toyoda, Kumiko Murayama, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Koji Izunome, Susumu Maeda, Kazuhiko Kashima
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Publication number: 20120139088Abstract: A silicon wafer for preventing a void defect in a bulk region from becoming source of contamination and slip generation in a device process is provided. And a heat-treating method thereof for reducing crystal defects such as COP in a region near the wafer surface to be a device active region is provided. The silicon wafer has a surface region 1 which is a defect-free region and a bulk region 2 including void defect of a polyhedron whose basic shape is an octahedron in which a corner portion of the polyhedron is in the curved shape and an inner-wall oxide film the void defect is removed. The silicon wafer is provided by performing a heat-treating method in which gas to be supplied, inner pressure of spaces and a maximum achievable temperature are set to a predetermined value when subjecting the silicon wafer produced by a CZ method to RTP.Type: ApplicationFiled: May 28, 2010Publication date: June 7, 2012Applicant: Covalent Materials CorporationInventors: Takeshi Senda, Hiromichi Isogai, Eiji Toyoda, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Koji Izunome, Susumu Maeda, Kazuhiko Kashima, Hiroyuki Saito
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Publication number: 20100197146Abstract: In a method of heat treating a wafer obtained by slicing a silicon single crystal ingot manufactured by the Czochralski method, a rapid heating/cooling heat treatment is carried out by setting a holding time at an ultimate temperature of 1200° C. or more and a melting point of silicon or less to be equal to or longer than one second and to be equal to or shorter than 60 seconds in a mixed gas atmosphere containing oxygen having an oxygen partial pressure of 1.0% or more and 20% or less and argon, and an oxide film having a thickness of 9.1 nm or less or 24.3 nm or more is thus formed on a surface of the silicon wafer.Type: ApplicationFiled: January 21, 2010Publication date: August 5, 2010Applicant: COVALENT MATERIALS CORPORATIONInventors: Takeshi Senda, Hiromichi Isogai, Eiji Toyoda, Kumiko Murayama, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Koji Izunome, Susumu Maeda, Kazuhiko Kashima
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Publication number: 20100038757Abstract: A silicon wafer produced from a silicon single crystal ingot grown by Czochralski process is subjected to rapid heating/cooling thermal process at a maximum temperature (T1) of 1300° C. or more, but less than 1380° C. in an oxidizing gas atmosphere having an oxygen partial pressure of 20% or more, but less than 100%. The silicon wafer according to the invention has, in a defect-free region (DZ layer) including at least a device active region of the silicon wafer, a high oxygen concentration region having a concentration of oxygen solid solution of 0.7×1018 atoms/cm3 or more and at the same time, the defect-free region contains interstitial silicon in supersaturated state.Type: ApplicationFiled: July 30, 2009Publication date: February 18, 2010Inventors: Hiromichi Isogai, Takeshi Senda, Eiji Toyoda, Kumiko Murayama, Koji Izunome, Susumu Maeda, Kazuhiko Kashima, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Yoichiro Mochizuki, Akihiko Kobayashi, Senlin Fu