Abstract: A method of accurately evaluating the metal contamination on silicon wafers by lifetime measurement. The silicon wafers are subjected to heat treatment and further to a corona charge as passivation, and then, the lifetime is measured, in which the heat treatment is at least one of the following processes that the silicon wafer is held at a temperature of 1250° C. or more to 1330° C. or less for 7 s or more to 220 s or less under an oxygen atmosphere and then the temperature is lowered at a rate of 30° C./s or more to 500° C./s or less, or that and the silicon wafer is held at a temperature of 1020° C. or more to less than 1250° C. for 7 s or more to 600 s or less under an oxygen atmosphere, and then the temperature is lowered at a rate of 1° C./s or more to 280° C./s or less.

Abstract: By accurately detecting cooling medium leakage in a heat treatment apparatus, reductions in yield and production efficiency are suppressed. A controller controls a lamp voltage or lamp current applied to a plurality of lamps based on the temperature of a semiconductor substrate detected by a temperature detector. When n is a positive integer of 2 or more, indicating the lot order of the semiconductor substrate to be treated, the controller calculates a difference effect size (n), based on the maximum lamp voltage or maximum lamp current applied to the plurality of lamps, according to equation below: Difference effect size(n)=(maximum lamp voltage or maximum lamp current(n)?maximum lamp voltage or maximum lamp current(n?1))/standard deviation of the maximum lamp voltage or maximum lamp current in a predetermined lot range, and determines that an abnormality has occurred when the difference effect size(n)exceeds a first threshold.

Abstract: The timing for removing granular SiOx deposits on an inner wall of a lamp sleeve is easily obtained to prevent a decrease in production efficiency and suppress an increase in power consumption for heat treatment. A heat treatment apparatus includes a plurality of lamps that heats a semiconductor substrate, a lamp sleeve that reflects irradiation light of the plurality of lamps; a power supply that applies a lamp voltage to the plurality of lamps; a temperature detector that detects a temperature of the semiconductor substrate, a controller that controls the lamp voltage or lamp current applied to the plurality of lamps, and a warning unit that makes a warning on timing for cleaning the lamp sleeve through a display or a voice. The controller causes the warning unit to issue a warning when the lamp voltage or lamp current applied to the plurality of lamps exceeds a predetermined threshold.

Abstract: A method of manufacturing a semiconductor wafer by performing the RTA treatment for suppressing slips is provided. The method of manufacturing a semiconductor wafer according to the present invention includes a step of performing the RTA treatment on a semiconductor wafer 1, wherein, for example, a first correction for eliminating temperature variations of the entire wafer surface is performed throughout the entire process of heating and cooling in the RTA treatment, and further, in the cooling process, a second correction of +0.1° C. or more and +5.0° C. or less is performed to a part or the entire wafer outer circumference 1d, which is an outer region including the wafer periphery.

Abstract: A method of manufacturing semiconductor wafers comprises the RTA process, wherein a wafer is placed on a wafer support member having a support surface inclined downwardly toward the inside, the RTA process is performed, and further wherein an angle between the wafer backside and the wafer backside bevel is formed at an obtuse angle, and the semiconductor wafer is processed so that the top of the obtuse angle contacts the support surface during the RTA process. During the RTA process, the angle ?1 of the angle between the wafer backside and the support surface and the angle ?2 of the angle between the backside bevel and the support surface formed at the contact position with the support surface are ?1?5° and ?2?5°, respectively, and the difference between the angles ?1 and ?2 is |?1??2|?5°, whereby the semiconductor wafer is produced.

Abstract: To provide a method of manufacturing silicon wafers having a low oxygen concentration and being provided with the gettering capability of heavy metals even when the density of BMD is low. The method includes a step of placing wafers sliced from a silicon single crystal and having an oxygen concentration in the range of 1×1016 atoms/cm3 to 7×1017 atoms/cm3, in a chamber and a step of performing rapid thermal processing at a maximum temperature reached of not less than 1250° C. or not more than 1350° C. after introducing a mixed gas having an oxygen partial pressure in the range of 1% to 10% of oxygen and an inert gas.

Abstract: A clean silicon wafer, having a DZ layer free of micro-defects formed in a device active region on the surface of the thermally-processed silicon wafer, an IG layer having a high gettering capability formed in a bulk layer, and little heavy metal contamination on the wafer surface is manufactured. A method for manufacturing a silicon wafer for performing the rapid thermal process for a silicon wafer in a furnace, the method performs the rapid thermal process with a thermal budget of 53% or more and 65% or less, in terms of a thermal budget with temperature and time, when a condition where a thermal process at a highest temperature of 1350° C. is maintained for a predetermined longest holding time is taken as 100% of the thermal budget.

Abstract: A silicon wafer is provided which is a Czochralski wafer formed of silicon, and a method for producing the silicon wafer are provided. The wafer includes a bulk layer having an oxygen concentration of 0.5×1018/cm3 or more; and a surface layer extending from the surface of the wafer to 300 nm in depth, and having an oxygen concentration of 2×1018/cm3 or more.

Abstract: Provided is a method for manufacturing a semiconductor silicon wafer capable of inhibiting P-aggregation defects (Si-P defects) and SF in an epitaxial layer. The method includes a step of forming a silicon oxide film with a thickness of at least 300 nm or thicker only on the backside of the silicon wafer substrate by the CVD method at a temperature of 500° C. or lower after the step of forming the silicon oxide film, a step of heat treatment where the substrate is kept in an oxidizing atmosphere at a constant temperature of 1100° C. or higher and 1250° C. or lower for 30 minutes or longer and 120 minutes or shorter after the heat treatment, a step of removing surface oxide film formed on the front surface of the substrate, and a step of depositing a silicon monocrystalline epitaxial layer on the substrate after the step of removing the surface oxide film.

Abstract: A processing temperature TS by a rapid thermal processing furnace is 1250° C. or more and 1350° C. or less, and a cooling rate Rd from the processing temperature is in a range of 20° C./s or more and 150° C./s or less, and thermal processing is performed by adjusting the processing temperature TS and the cooling rate Rd within a range between the upper limit P=0.00207TS·Rd?2.52Rd+13.3 (Formula (A)) and the lower limit P=0.000548TS·Rd?0.605Rd?0.511 (Formula (B)) of an oxygen partial pressure P in a thermal processing atmosphere.

Abstract: An evaluation method of a silicon wafer allows non-destructive and non-contact inspection of a slip that affects the electrical properties of semiconductor devices, without being subjected to restrictions of the surface condition of silicon wafers or processing contents as much as possible. The evaluation method of a silicon wafer includes a step of section analysis where a surface of a single crystal silicon wafer after thermal processing is divided by equally-spaced lines into sections with an area of 1 mm2 or more and 25 mm2 or less and the existence of strain in each of the sections is determined based on a depolarization value of polarized infrared light, and a screening step where the wafer is evaluated as non-defective when the number of adjacent sections being determined to have strain by the section analysis step does not exceed a predetermined threshold value.

Abstract: An evaluation method of a silicon wafer allows non-destructive and non-contact inspection of a slip that affects the electrical properties of semiconductor devices, without being subjected to restrictions of the surface condition of silicon wafers or processing contents as much as possible. The evaluation method of a silicon wafer includes a step of section analysis where a surface of a single crystal silicon wafer after thermal processing is divided by equally-spaced lines into sections with an area of 1 mm2 or more and 25 mm2 or less and the existence of strain in each of the sections is determined based on a depolarization value of polarized infrared light, and a screening step where the wafer is evaluated as non-defective when the number of adjacent sections being determined to have strain by the section analysis step does not exceed a predetermined threshold value.

Abstract: A processing temperature TS by a rapid thermal processing furnace is 1250° C. or more and 1350° C. or less, and a cooling rate Rd from the processing temperature is in a range of 20° C./s or more and 150° C./s or less, and thermal processing is performed by adjusting the processing temperature TS and the cooling rate Rd within a range between the upper limit P=0.00207TS·Rd?2.52Rd+13.3 (Formula (A)) and the lower limit P=0.000548TS·Rd?0.605Rd?0.511 (Formula (B)) of an oxygen partial pressure P in a thermal processing atmosphere.

Abstract: A silicon wafer includes a denuded zone which is a surface layer and of which the density of vacancy-oxygen complexes which are complexes of vacancies and oxygen is less than 1.0×1012/cm3. An intermediate layer is disposed inwardly of the denuded zone so as to be adjacent to the denuded zone. The density of the vacancy-oxygen complexes in the intermediate layer increases gradually inwardly in the depth direction from the boundary with the denuded zone within a range of 1.0×1012/cm3 or over and less than 5.0×1012/cm3. The intermediate layer has a depth determined corresponding to the depth of the denuded zone. A bulk layer is disposed inwardly of the intermediate layer so as to be adjacent to the intermediate layer. The density of the vacancy-oxygen complexes in the bulk layer is 5.0×1012/cm3 or over.

Abstract: A silicon wafer includes a denuded zone which is a surface layer and of which the density of vacancy-oxygen complexes which are complexes of vacancies and oxygen is less than 1.0×1012/cm3. An intermediate layer is disposed inwardly of the denuded zone so as to be adjacent to the denuded zone. The density of the vacancy-oxygen complexes in the intermediate layer increases gradually inwardly in the depth direction from the boundary with the denuded zone within a range of 1.0×1012/cm3 or over and less than 5.0×1012/cm3. The intermediate layer has a depth determined corresponding to the depth of the denuded zone. A bulk layer is disposed inwardly of the intermediate layer so as to be adjacent to the intermediate layer. The density of the vacancy-oxygen complexes in the bulk layer is 5.0×1012/cm3 or over.

Abstract: A silicon wafer is manufactured by subjecting a silicon wafer sliced from a silicon single-crystal ingot grown by the Czochralski process to a rapid thermal process in which the silicon wafer is heated to a maximum temperature within a range of 1300 to 1380° C., and kept at the maximum temperature for 5 to 60 seconds; and removing a surface layer of the wafer where a semiconductor device is to be manufactured by a thickness of not less X [?m] which is calculated according to the below equations (1) to (3): X [?m]=a [?m]+b [?m]??(1); a [?m]=(0.0031×(said maximum temperature) [° C.]?3.1)×6.4×(cooling rate)?0.4 [° C./second]??(2); and b [?m]=a/(solid solubility limit of oxygen) [atoms/cm3]/(oxygen concentration in substrate) [atoms/cm3]??(3).

Abstract: Provided is a method for manufacturing a silicon wafer including a first step of heat-treating a raw silicon wafer sliced from a silicon single crystal ingot grown by the Czochralski method in an oxidizing gas atmosphere at a maximum target temperature of 1300 to 1380° C., a second step of removing an oxide film on a surface of the heated-treated silicon wafer obtained in the first step, and a third step of heat-treating the stripped silicon wafer obtained in the second step in a non-oxidizing gas atmosphere at a maximum target temperature of 1200 to 1380° C. and at a heating rate of 1° C./sec to 150° C./sec in order that the silicon wafer may have a maximum oxygen concentration of 1.3×1018 atoms/cm3 or below in a region from the surface up to 7 ?m in depth.

Abstract: A silicon wafer for preventing a void defect in a bulk region from becoming source of contamination and slip generation in a device process is provided. And a heat-treating method thereof for reducing crystal defects such as COP in a region near the wafer surface to be a device active region is provided. The silicon wafer has a surface region 1 which is a defect-free region and a bulk region 2 including void defect of a polyhedron whose basic shape is an octahedron in which a corner portion of the polyhedron is in the curved shape and an inner-wall oxide film the void defect is removed. The silicon wafer is provided by performing a heat-treating method in which gas to be supplied, inner pressure of spaces and a maximum achievable temperature are set to a predetermined value when subjecting the silicon wafer produced by a CZ method to RTP.

Abstract: A silicon wafer is manufactured by subjecting a silicon wafer sliced from a silicon single-crystal ingot grown by the Czochralski process to a rapid thermal process in which the silicon wafer is heated to a maximum temperature within a range of 1300 to 1380° C., and kept at the maximum temperature for 5 to 60 seconds; and removing a surface layer of the wafer where a semiconductor device is to be manufactured by a thickness of not less X [?m] which is calculated according to the below equations (1) to (3): X[?m]=a[?m]+b[?m]??(1); a[?m]=(0.0031×(said maximum temperature)[° C.]?3.1)×6.4×(cooling rate)?0.4[° C./second] . . . (2); and b[?m]=a/(solid solubility limit of oxygen) [atoms/cm3]/(oxygen concentration in substrate) [atoms/cm3]??(3).

Abstract: A silicon wafer produced from a silicon single crystal ingot grown by Czochralski process is subjected to rapid heating/cooling thermal process at a maximum temperature (T1) of 1300° C. or more, but less than 1380° C. in an oxidizing gas atmosphere having an oxygen partial pressure of 20% or more, but less than 100%. The silicon wafer according to the invention has, in a defect-free region (DZ layer) including at least a device active region of the silicon wafer, a high oxygen concentration region having a concentration of oxygen solid solution of 0.7×1018 atoms/cm3 or more and at the same time, the defect-free region contains interstitial silicon in supersaturated state.