Abstract: With a view to realizing a titanium oxide structure that has a large surface area and enables efficient transfer of ions and electrons by virtue of titanium oxide particles connected to one another, an object of the invention is to develop a material useful as an active material for dye-sensitized solar cells, and a process for producing the material; a porous titanium oxide composition and a process for producing the composition; and a photoelectric conversion element comprising the titanium oxide structure or porous titanium oxide composition.

Abstract: With a view to realizing a titanium oxide composite that has a large surface area and that enables efficient transfer of electrons by covering a surface of rod-like or fibrous carbon with a covering layer comprising titanium oxide particles connected to one another, an object of the invention is to develop a material useful as an active material for dye-sensitized solar cells, and a process for producing the material; a porous titanium oxide-covered carbon material composition, and a process for producing the composition; and a photoelectric conversion element comprising the titanium oxide-covered carbon material or porous titanium oxide-covered carbon material composition.

Abstract: With a view to realizing a titanium oxide structure that has a large surface area and enables efficient transfer of ions and electrons by virtue of titanium oxide particles connected to one another, an object of the invention is to develop a material useful as an active material for dye-sensitized solar cells, and a process for producing the material; a porous titanium oxide composition and a process for producing the composition; and a photoelectric conversion element comprising the titanium oxide structure or porous titanium oxide composition.

Abstract: According to one embodiment, an information processing apparatus includes a CPU including a plurality of instruction processors, a monitoring unit which monitors an operating power supplying environment, and a power saving unit which controls the number of operating instruction processors provided in the CPU in accordance with the operating power supplying environment obtained by the monitoring with the monitoring unit.

Abstract: According to one embodiment, a virtual processing portion, which has a work processing portion that issues a request for process using a hardware resource and which operates as a virtual computer, includes a hardware resource managing portion having a manager that collectively manages hardware resources of respective information processing apparatuses connected to the network and that is configured to transmit the request for process to one of the information processing apparatuses capable of performing the process in accordance with the request and to acquire a result of process. A second virtual process monitoring portion is configured to receive the request issued from the work processing portion, transfer the request to the hardware resource managing portion if the request satisfies a certain condition, receive the result of process corresponding to the request from the hardware resource managing portion and transfer the result of process to the work processing portion.

Abstract: A controller refers to an address translation table and searches for the logical address of a valid logical block used by a host computer. Then, the controller reads from a disk array only a physical stripe that includes the physical block of a physical address corresponding to the valid logical address. Based on the read physical stripe, the controller restores data of a failing disk drive and writes the restored data in a spare disk drive that is used in place of the failing disk drive.

Abstract: A controller retrieves effective logical addresses sequentially according to a copy of an address translation table at the time of the start of storage capacity expansion in the process of expanding the storage capacity of a disk array by adding a disk drive to the disk array. The controller stores the data in the logical address into a restructured write buffer each time an effective logical address is retrieved. The controller writes one stripe worth of data blocks including one stripe of logical blocks and a logical address tag block into an empty area different from the area in which the data to be updated has been stored in the data array each time one stripe worth of logical blocks of data is accumulated in the write buffer.

Abstract: At the start of a backup operation, the controller of a disk array apparatus makes a copy of an address translation table and searches for a valid logical address based on the copy. From the disk array, the controller reads a physical stripe including a data block of a physical address corresponding to the valid logical address searched for. The controller writes a data block corresponding to a valid logical address included in the read physical stripe in a mass storage device.

Abstract: A controller uses an address translation table to search for a logical address of a valid logical block used by a host computer. The controller then loads from a disk array only a physical stripe containing a physical block with a physical address corresponding to the valid logical address. The controller performs parity processing for only the loaded physical stripe.

Abstract: In writing all logical blocks in a data stripe in a disk array, a controller generates a logical address tag block corresponding to these logical blocks. The controller stores the logical address tag block in logical address tag block areas ensured other than data areas on the disk array which store the data stripe.

Abstract: For file access upon file reference (read request) without any file content update (data update) process, a write process for writing an i node of that file on a disk device is not executed (no write request is generated), and “i node latest access time” is updated on a kernel space to manage the i node.

Abstract: A controller retrieves effective logical addresses sequentially according to a copy of an address translation table at the time of the start of storage capacity expansion in the process of expanding the storage capacity of a disk array by adding a disk drive to the disk array. The controller stores the data in the logical address into a restructured write buffer each time an effective logical address is retrieved. The controller writes one stripe worth of data blocks including one stripe of logical blocks and a logical address tag block into an empty area different from the area in which the data to be updated has been stored in the data array each time one stripe worth of logical blocks of data is accumulated in the write buffer.

Abstract: At the start of a backup operation, the controller of a disk array apparatus makes a copy of an address translation table and searches for a valid logical address based on the copy. From the disk array, the controller reads a physical stripe including a data block of a physical address corresponding to the valid logical address searched for. The controller writes a data block corresponding to a valid logical address included in the read physical stripe in a mass storage device.

Abstract: In writing all logical blocks in a data stripe in a disk array, a controller generates a logical address tag block corresponding to these logical blocks. The controller stores the logical address tag block in logical address tag block areas ensured other than data areas on the disk array which store the data stripe.

Abstract: A controller refers to an address translation table and searches for the logical address of a valid logical block used by a host computer. Then, the controller reads from a disk array only a physical stripe that includes the physical block of a physical address corresponding to the valid logical address. Based on the read physical stripe, the controller restores data of a failing disk drive and writes the restored data in a spare disk drive that is used in place of the failing disk drive.

Abstract: A controller uses an address translation table to search for a logical address of a valid logical block used by a host computer. The controller then loads from a disk array only a physical stripe containing a physical block with a physical address corresponding to the valid logical address. The controller performs parity processing for only the loaded physical stripe.

Abstract: There is provided a foamed article having a low density, large thickness, a high closed cell ratio and a small average cell diameter. A foamed extrusion article having a density of 50 to 10 kg/m3 and a closed cell ratio of at least 40% is obtained by mixing a mixed resin comprising (a) 50 to 95 parts by weight of a polypropylene resin having a melt tension at 230° C. of at least 0.05 N, (b) 50 to 5 parts by weight of a polystyrene resin, and (c) 0.5 to 15.0 parts by weight of a hydrogenated block copolymer of styrene, isoprene and styrene based on 100 parts by weight of the polypropylene resin (a) and the polystyrene resin (b) with a foaming agent in an extruder, and then releasing into a low-pressure zone.

Abstract: A disk storage system with a RAID architecture includes a write buffer having a storage capacity corresponding to one stripe, a buffer management table, and a controller. The controller stores, in the write buffer, logical blocks whose data lengths are changed, as needed, and delays updating of the logical blocks stored in the write buffer in data update processing until the number of stored logical blocks reaches N*K−1 The controller then performs a continuous write operation to sequentially write N*K logical blocks, obtained by adding a logical address tag block to the N*K−1logical blocks, in contiguous areas of empty areas different from the areas in which the old data are stored.

Abstract: The present invention relates to a siloxane random copolymer having a repeating unit represented by the following general formula (I) (II) and (III) at random and a resin composition containing the same. ##STR1## Further, the invention relates to a process of producing a siloxane copolymer comprising the step of reacting at least one polycarbonate and/or dicarbonate of diol and, if needed, at least one diester of dicarboxylic acid with at least one specified silicon compound in the presence of an esterifying or ester exchange catalyst.

Abstract: The present invention relates to a foamed article comprising a modified polypropylene resin which is a graft copolymer of a polypropylene resin and an aromatic vinyl monomer and has an average number of the grafted aromatic vinyl chains of not less than 1 in one molecule of the graft copolymer and a weight average molecular weight of the grafted aromatic vinyl chains of not less than 200, and relates to a process for preparation thereof. According to the present invention, the foamed article comprising the polypropylene resin and having a high closed cell content, a high expansion ratio and good external appearance can be provided.