Patents by Inventor Haruo Wakai
Haruo Wakai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6744416Abstract: A field sequential type liquid crystal display apparatus includes a liquid crystal display device in which unit-color image data of different colors are sequentially written in display elements during the period of one frame composed of three continuous fields, and an illuminating unit placed at the back of the liquid crystal display device to sequentially emit light beams having colors corresponding to the colors of the unit-color image data in accordance with the sequential write of the unit-color image data. The illuminating device is selectively controlled to sequential turn-on of colors, total turn-off by which the emission of all the light beams is stopped, or total turn-on. A semitransparent reflecting film is formed between the liquid crystal display device and the illuminating unit.Type: GrantFiled: December 21, 2001Date of Patent: June 1, 2004Assignee: Casio Computer Co., Ltd.Inventors: Yasushi Mizutani, Hisashi Aoki, Haruo Wakai, Shingo Yamauchi
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Publication number: 20020113761Abstract: A field sequential type liquid crystal display apparatus includes a liquid crystal display device in which unit-color image data of different colors are sequentially written in display elements during the period of one frame composed of three continuous fields, and an illuminating unit placed at the back of the liquid crystal display device to sequentially emit light beams having colors corresponding to the colors of the unit-color image data in accordance with the sequential write of the unit-color image data. The illuminating device is selectively controlled to sequential turn-on of colors, total turn-off by which the emission of all the light beams is stopped, or total turn-on. A semitransparent reflecting film is formed between the liquid crystal display device and the illuminating unit.Type: ApplicationFiled: December 21, 2001Publication date: August 22, 2002Applicant: Casio Computer Co., Ltd.Inventors: Yasushi Mizutani, Hisashi Aoki, Haruo Wakai, Shingo Yamauchi
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Patent number: 5821137Abstract: A thin film transistor including a thin semiconductor film which has a central portion as a channel region, with the side portions of the semiconductor film except for the channel region being a source and a drain regions which includes n-type impurities such as phosphorus ions of high concentration (3.times.10.sup.15 atoms/cm.sup.2), and a low concentration region provided between the channel region and each of the source and drain regions including p-type impurities such as boron ions of a low concentration (1.times.10.sup.13 atoms/cm.sup.2) whereby the low concentration region serves to reduce the off current.Type: GrantFiled: May 15, 1995Date of Patent: October 13, 1998Assignee: Casio Computer Co., Ltd.Inventors: Haruo Wakai, Shinichi Shimomaki, Tatuya Miyakawa
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Patent number: 5736436Abstract: A gate electrode, a semiconductor thin film, a channel protecting film and a photoresist are accumulated on the overall surface of a transparent substrate on which a gate electrode and a gate line are formed. Ultraviolet rays are irradiated through the substrate so that the photoresist and the channel protecting film are self-aligned with respect to the gate electrode and the gate line. A mask is formed on the channel protecting film so as to extend in a direction perpendicular to the channel protecting film. The channel protecting film and the semiconductor thin film are etched using the mask. As a result, the semiconductor thin film and the channel protecting film are patterned without positional deviation so as to have the same width W. Therefore, it is possible to reduce the thin film transistor forming region and the number of steps of the manufacturing process.Type: GrantFiled: November 20, 1995Date of Patent: April 7, 1998Assignee: Casio Computer Co., Ltd.Inventors: Hiroshi Matsumoto, Haruo Wakai, Hiroyasu Joubettou
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Patent number: 5694061Abstract: A semiconductor device having at least first and second MIS transistors of a same P or N conductive type. The first MIS transistor has a first data terminal which receives a high potential Vdd, and the second MIS transistor has a first data terminal which receives a low potential GND lower than the high potential Vdd. An output terminal is coupled to second data terminals of the first and second MIS transistors. A first input terminal is connected to a gate of the first MIS transistor for supplying a non-inverted signal. A second input terminal is directly connected to a gate of one of the first and second MIS transistors for supplying an inverted signal having a reverse polarity to the non-inverted signal and which is synchronized with the non-inverted signal. An output voltage compensating circuit is connected between one of (i) the output terminal and the first input terminal and (ii) the output terminal and the second input terminal.Type: GrantFiled: March 22, 1996Date of Patent: December 2, 1997Assignee: Casio Computer Co., Ltd.Inventors: Katsuhiko Morosawa, Haruo Wakai
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Patent number: 5545576Abstract: A gate electrode, a semiconductor thin film, a channel protecting film and a photoresist are accumulated on the overall surface of a transparent substrate on which a gate electrode and a gate line are formed. Ultraviolet rays are irradiated through the substrate so that the photoresist and the channel protecting film are self-aligned with respect to the gate electrode and the gate line. A mask is formed on the channel protecting film so as to extend in a direction perpendicular to the channel protecting film. The channel protecting film and the semiconductor thin film are etched using the mask. As a result, the semiconductor thin film and the channel protecting film are patterned without positional deviation so as to have the same width W. Therefore, it is possible to reduce the thin film transistor forming region and the number of steps of the manufacturing process.Type: GrantFiled: April 21, 1995Date of Patent: August 13, 1996Assignee: Casio Computer Co., Ltd.Inventors: Hiroshi Matsumoto, Haruo Wakai, Hiroyasu Joubettou
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Patent number: 5477073Abstract: A thin film transistor including a thin semiconductor film which has a central portion as a channel region, with the side portions of the semiconductor film except for the channel region being a source and a drain regions which includes n-type impurities such as phosphorus ions of high concentration (3.times.10.sup.15 atoms/cm.sup.2), and a low concentration region provided between the channel region and each of the source and drain regions including p-type impurities such as boron ions of a low concentration (1.times.10.sup.13 atoms/cm.sup.2) whereby the low concentration region serves to reduce the off current.Type: GrantFiled: August 9, 1994Date of Patent: December 19, 1995Assignee: Casio Computer Co., Ltd.Inventors: Haruo Wakai, Shinichi Shimomaki, Tatuya Miyakawa
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Patent number: 5424230Abstract: An amorphous silicon hydride thin film is deposited on an insulating body by a plasma CVD method, and is then heated for dehydrogenating the amorphous silicon thin film so that a dehydrogenated amorphous silicon thin film containing hydrogen of 3 atomic % or less is formed. The insulating body may be an insulating substrate (such as a glass substrate) alone, or a combination of an insulating substrate with an intermediate insulating base layer thereon. Impurity ions are injected into the dehydrogenated amorphous silicon hydride thin film to form source and drain regions. Excimer laser beams are applied to the dehydrogenated amorphous silicon thin film, thereby polycrystallizing the amorphous silicon thin film into a polysilicon thin film and activating the injected impurity ions.Type: GrantFiled: July 29, 1994Date of Patent: June 13, 1995Assignee: Casio Computer Co., Ltd.Inventor: Haruo Wakai
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Patent number: 5327001Abstract: A TFT array has a plurality of gate lines and a plurality of drain lines formed on a transparent insulating substrate. The gate lines intersect with the drain lines. TFTs are formed at the intersections of the gate lines and the drain lines. An opaque film is formed above the gate lines, the drain lines, and the TFTs, allowing no passage of light passing through the gaps between the transparent electrode, on the one hand, and the gate and drain lines, on the other hand. Therefore, when the TFT array is incorporated into a liquid-crystal display, the display will display high-contrast images.Type: GrantFiled: April 1, 1993Date of Patent: July 5, 1994Assignee: Casio Computer Co., Ltd.Inventors: Haruo Wakai, Nobuyuki Yamamura, Syunichi Sato, Minoru Kanbara
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Patent number: 5229644Abstract: A TFT is formed on a transparent insulative substrate, and includes a gate electrode, a gate insulating film, a semiconductor film which has a channel portion, source and drain electrodes. An insulating film is formed on the TFT so as to cover at least the drain electrode and the gate insulating film. A transparent electrode is formed on at least part of insulating film except for a portion above the channel portion on the semiconductor film. The transparent electrode is electrically connected to the source electrode via a through hole which is formed on the insulating film at a position of the source electrode.Type: GrantFiled: February 5, 1992Date of Patent: July 20, 1993Assignee: Casio Computer Co., Ltd.Inventors: Haruo Wakai, Nobuyuki Yamamura, Syunichi Sato, Minoru Kanbara
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Patent number: 5166085Abstract: First, a gate metal layer, a gate insulating film, a semiconductor layer, an n-type semiconductor layer, and an ohmic metal layer formed on a substrate in the order mentioned. Then, the film and the layers are patterned into those having the same shape and size. Next, a source metal layer and a drain metal layer are formed on the ohmic metal layer. Further, a portion of the ohmic metal layer, a portion of said source metal layer, and a portion of said drain metal layer are etched, thereby forming a channel portion. Finally, a transparent electrode is formed on the source metal layer, thus manufacturing a TFT. Since the film and the layer, the major components of the TFT, are sequentially formed, and are patterned simultaneously, the TFT can be manufacture with high yield. Further, since the transparent electrode is formed on the uppermost layer, i.e., the source metal layer, the pixel has a great opening ratio.Type: GrantFiled: April 2, 1990Date of Patent: November 24, 1992Assignee: Casio Computer Co., Ltd.Inventors: Haruo Wakai, Nobuyuki Yamamura, Syunichi Sato, Minoru Kanbara
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Patent number: 5060034Abstract: A memory device includes a memory element composed of a first thin film transistor having a memory function, and a select element composed of a second thin film transistor for selecting the memory element. A gate insulation film of the first thin film transistor has a charge storage function. A gate insulation film of the second thin film transistor does not have any charge storage function. If a plurality of the memory devices are arranged in matrix form, this configuration can be used as E.sup.2 PROM. By forming the first and second thin film transistors simultaneously, it is possible to form the first and second thin film transistors easily in the simple manufacturing steps.Type: GrantFiled: October 25, 1989Date of Patent: October 22, 1991Assignee: Casio Computer Co., Ltd.Inventors: Hideaki Shimizu, Nobuyuki Yamamura, Hiroyasu Yamada, Haruo Wakai, Hiroshi Matsumoto
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Patent number: 5055899Abstract: A thin film transistor comprising a gate electrode, a gate insulating film, and a semiconductor layer, which have the same shape and the same size and stacked one upon another. The transistor further comprises an n-type semiconductor layer formed on the semiconductor layer, an ohmic electrode formed on the n-type semiconductor layer, and a source electrode and a drain electrode both formed on the ohmic electrode. Further, a transparent electrode is electrically connected to the source electrode. The thin film transistor has no step portions. Therefore, the transistor can be manufactured with high yield, and forms a pixel having a high opening ratio.Type: GrantFiled: April 2, 1990Date of Patent: October 8, 1991Assignee: Casio Computer Co., Ltd.Inventors: Haruo Wakai, Nobuyuki Yamamura, Syunichi Sato, Minoru Kanbara
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Patent number: 5032883Abstract: A TFT of the present invention includes a transparent insulative substrate, a gate electrode formed on the substrate, a gate insulating film formed on at least the gate electrode, a semiconductor film formed at a position on the gate insulating film corresponding to the gate electrode, source and drain electrodes arranged on the semiconductor film so as to form a channel portion, a transparent insulating film covering the source and drain electrodes and the semiconductor film, and a transparent electrode connected to the source electrode. A through hole is formed in the transparent insulating film above the source electrode. The transparent electrode is formed on a portion of the transparent insulating film except for a portion above the channel portion on the semiconductor film.Type: GrantFiled: September 7, 1988Date of Patent: July 16, 1991Assignee: Casio Computer Co., Ltd.Inventors: Haruo Wakai, Nobuyuki Yamamura, Syunichi Sato, Minoru Kanbara
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Patent number: 5003356Abstract: A TFT array having a plurality of gate lines and a plurality of drain lines formed on a transparent substrate. The gate lines intersect with the drain lines. TFT are formed at the intersections of the gate lines and the drain lines. An insulating film is formed on the drain lines and the drain electrodes of the TFTs. Pixel electrodes are formed, each overlapping the corresponding gate line and the corresponding drain line. The pixel electrode has a large area and thus, have a high opening ratio. The TFT array can, therefore, help to provide a liquid crystal display having high contrast.Type: GrantFiled: April 2, 1990Date of Patent: March 26, 1991Assignee: Casio Computer Co., Ltd.Inventors: Haruo Wakai, Nobuyuki Yamamura, Syunichi Sato, Minoru Kanbara