Patents by Inventor Haruo Yamakoshi

Haruo Yamakoshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220393586
    Abstract: A semiconductor device includes: an operational amplifier; an external terminal configured to be attached to an external capacitor; and a resistor configured to be connected between a node, to which an output terminal and an inverting input terminal of the operational amplifier are connected in common, and the external terminal.
    Type: Application
    Filed: May 12, 2022
    Publication date: December 8, 2022
    Inventor: Haruo Yamakoshi
  • Patent number: 10958269
    Abstract: A bridge output circuit of the present invention reduces the dead time. Upon receiving an input signal (SIN) for indicating on state of a high-side transistor (1H), a gate control signal generation circuit (4) outputs a low-side gate control signal (LGCTL) for turning off a low-side transistor (1L) to a low-side driver circuit (2L). On the other hand, a high-side gate control signal (HGCTL) for turning on the high-side transistor is generated from a signal delayed the low-side gate control signal and outputted to a high-side driver circuit (2H). The time of delay is controlled by the input signal (SIN), a signal (LGFB) indicating on/off state of the low-side transistor, and a signal (SOUT_L) indicating a level of an output signal.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: March 23, 2021
    Assignee: Rohm Co., Ltd.
    Inventor: Haruo Yamakoshi
  • Publication number: 20200252062
    Abstract: A bridge output circuit of the present invention reduces the dead time. Upon receiving an input signal (SIN) for indicating on state of a high-side transistor (1H), a gate control signal generation circuit (4) outputs a low-side gate control signal (LGCTL) for turning off a low-side transistor (1L) to a low-side driver circuit (2L). On the other hand, a high-side gate control signal (HGCTL) for turning on the high-side transistor is generated from a signal delayed the low-side gate control signal and outputted to a high-side driver circuit (2H). The time of delay is controlled by the input signal (SIN), a signal (LGFB) indicating on/off state of the low-side transistor, and a signal (SOUT_L) indicating a level of an output signal.
    Type: Application
    Filed: January 31, 2020
    Publication date: August 6, 2020
    Applicant: Rohm Co., Ltd.
    Inventor: Haruo Yamakoshi
  • Patent number: 8686705
    Abstract: A current mode synchronous rectification direct current (DC)/DC converter according to the present invention includes: a soft start function unit (in FIG. 1, a reference voltage generation unit (104) enabling a reference voltage REF to slowly increase while starting), for inhibiting a target value of an output voltage VO to be lower than that at a normal action while starting; and an output stabilization function unit (in FIG. 1, a frequency variable type oscillator (110A) generating a clock signal CLK and a slope voltage SLOPE through an oscillation frequency corresponding to a reference voltage REF), for performing at least one of waiting for start of a switching action and reduction of a drive frequency while starting.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: April 1, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Haruo Yamakoshi, Hirotaka Nakabayashi
  • Publication number: 20120126772
    Abstract: A current mode synchronous rectification direct current (DC)/DC converter according to the present invention includes: a soft start function unit (in FIG. 1, a reference voltage generation unit (104) enabling a reference voltage REF to slowly increase while starting), for inhibiting a target value of an output voltage VO to be lower than that at a normal action while starting; and an output stabilization function unit (in FIG. 1, a frequency variable type oscillator (110A) generating a clock signal CLK and a slope voltage SLOPE through an oscillation frequency corresponding to a reference voltage REF), for performing at least one of waiting for start of a switching action and reduction of a drive frequency while starting.
    Type: Application
    Filed: November 22, 2011
    Publication date: May 24, 2012
    Inventors: Haruo Yamakoshi, Hirotaka Nakabayashi