Abstract: According to an embodiment, a storage control device includes a controller, a compression condition determiner, a compressor, and an error correction encoder. The controller receives a write request for a data item and determines whether or not the wear degree of a target region in a storage device to which the data item is to be written is less than a threshold value. The compression condition determiner determines, based on the wear degree, an optimal compression condition out of compression conditions that include lossy compression. The compressor generates, based on the compression condition, compressed data. The error correction encoder subjects the data item to error correction and generates encoded data.

Abstract: According to an embodiment, a storage control device includes a controller, a compression condition determiner, a compressor, and an error correction encoder. The controller receives a write request for a data item and determines whether or not the wear degree of a target region in a storage device to which the data item is to be written is less than a threshold value. The compression condition determiner determines, based on the wear degree, an optimal compression condition out of compression conditions that include lossy compression. The compressor generates, based on the compression condition, compressed data. The error correction encoder subjects the data item to error correction and generates encoded data.

Abstract: A semiconductor integrated circuit device includes a first semiconductor device and a second semiconductor device, first and second buffer circuits, a data bus, and a control circuit. The semiconductor integrated circuit device executes data transmission/reception between the first and second semiconductor devices. The first and second buffer circuits store data. The data bus transmits the data between the first and second buffer circuits. The first semiconductor device reads out the transfer data into the first buffer circuit. The control circuit transfers the transfer data, which is stored in the first buffer circuit, to the second buffer circuit via the data bus. The control circuit acquires a right of use of the data bus after the first semiconductor device writes the transfer data into the first buffer circuit, and disclaims the right of use of the data bus after the transfer data is transferred to the second buffer circuit.

Abstract: A semiconductor integrated circuit device includes a first semiconductor device and a second semiconductor device, first and second buffer circuits, a data bus, and a control circuit. The semiconductor integrated circuit device executes data transmission/reception between the first and second semiconductor devices. The first and second buffer circuits store data. The data bus transmits the data between the first and second buffer circuits. The first semiconductor device reads out the transfer data into the first buffer circuit. The control circuit transfers the transfer data, which is stored in the first buffer circuit, to the second buffer circuit via the data bus. The control circuit acquires a right of use of the data bus after the first semiconductor device writes the transfer data into the first buffer circuit, and disclaims the right of use of the data bus after the transfer data is transferred to the second buffer circuit.

Abstract: A first storage unit stores an address of a branching instruction and a branched address. A first detector detects whether or not an instruction of the present address has previously been branched from an output of the first storage unit. When the first detector detects previous branching of the instruction of the present address, the second storage unit stores the branched address corresponding to the address of the instruction to be executed following the branching instruction. When a second detector detects an output of a program counter as the address of the instruction to be executed following the branching instruction, the second storage unit outputs the branched address.

Abstract: A semiconductor integrated circuit device includes a first semiconductor device and a second semiconductor device, first and second buffer circuits, a data bus, and a control circuit. The semiconductor integrated circuit device executes data transmission/reception between the first and second semiconductor devices. The first and second buffer circuits store data. The data bus transmits the data between the first and second buffer circuits. The first semiconductor device reads out the transfer data into the first buffer circuit. The control circuit transfers the transfer data, which is stored in the first buffer circuit, to the second buffer circuit via the data bus. The control circuit acquires a right of use of the data bus after the first semiconductor device writes the transfer data into the first buffer circuit, and disclaims the right of use of the data bus after the transfer data is transferred to the second buffer circuit.

Abstract: A data processing apparatus that reduces a fanout load of a control signal for controlling a pipeline includes a first pipeline processing portion for executing a processing in five divided stages, a second pipeline processing portion for executing a processing one stage behind the first pipeline processing portion, and a plurality of flip-flops for latching the control signals inputted to the respective stages. The second pipeline processing portion performs the processing in each stage based on delayed control signals generated by once latching the control signals inputted to the respective stages by the flip-flop, thereby reducing the fanout load and signal delay of the control signals. Moreover, a wiring length of a control line for transmitting the control signals can be set to be longer than a conventional wiring length.

Abstract: A processor with a register renaming function comprises: an instruction fetch; a decoder for an instruction code of a fetched instruction; a register holding data corresponding to a register number; a register body holding data corresponding to a register number; a caching register to cache the contents in the body; an inner instruction information holder (IIIH) to hold information on a state of an inner instruction including a logical register number and a caching register number of the caching register by the fetched instruction; an instruction insertion determiner (IID) to compare an instruction code by pre-decoding the fetched instruction with information on a state of the inner instruction of IIIH to determine the inner instruction; and a register transfer instruction issuer for transferring inner data between the caching register and the body when the IID determines the inner transfer instruction is to be inserted.

Abstract: A first storage unit stores an address of a branching instruction and a branched address. A first detector detects whether or not an instruction of the present address has previously been branched from an output of the first storage unit. When the first detector detects previous branching of the instruction of the present address, the second storage unit stores the branched address corresponding to the address of the instruction to be executed following the branching instruction. When a second detector detects an output of a program counter as the address of the instruction to be executed following the branching instruction, the second storage unit outputs the branched address.

Abstract: This invention provides a data transfer method and a data transfer apparatus employing simple hardware to transfer data between two circuits operating at different clock frequencies with reduced data transfer overhead so as to shorten transfer delay time. The data transfer method and apparatus generate a data transfer reference signal involving a pulse that is within a cycle of a lower one of the clock frequencies and is synchronized with a pulse of a higher one of the clock frequencies. When transferring data between the two circuits, one of the circuits serving as a source circuit uses the data transfer reference signal to determine whether or not the other circuit serving as a destination circuit has completely received data transferred from the source circuit. The method and apparatus are capable of speedily transferring data and quickly recognizing the completion of data transfer.

Abstract: There is disclosed a data processing apparatus which can reduce fanout load of a control signal for controlling a pipeline. The data processing apparatus of the present invention includes a first pipeline processing portion for executing a processing in five divided stages, a second pipeline processing portion for executing a processing one stage behind the first pipeline processing portion, and a plurality of flip-flops for latching the control signals inputted to the respective stages. The second pipeline processing portion performs the processing in each stage based on delayed control signals Control-A to E generated by once latching the control signals Control-A to E inputted to the respective stages by the flip-flop. Because of this, the fanout load of the control signals Control-A to E is reduced, and signal delay of the control signals Control-A to E can be reduced.

Abstract: A microprocessor has a CPU, cache memories including TLBs, an internal memory control section (IMC) for controlling the data access operation to the cache memories, an external bus controller for controlling the data input/output operation between external memories and the cache memories, a first group of internal buses for connecting the CPU, the cache memories and IMC, and for transferring logical addresses, logical data and data among the CPU and the cache memories, and a second group of internal buses for connecting the cache memories, IMC and the external bus controller, and for transferring data among the cache memories and the external memories. Each cache memory and IMC are connected to the first group of internal buses and to the second group of internal buses in parallel, and the IMC controls the use of the second group of internal buses, and the data input/output operation to the group of the internal memories.