Patents by Inventor Harutaka Makabe

Harutaka Makabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240331794
    Abstract: Self-test circuits of memory devices disclosed herein may include circuitry that adjusts the correspondence between logical and physical addresses to match pre-repair mapping of memory locations. That is, if a memory device has been repaired by remapping logical addresses to new physical addresses, the circuitry of the test circuit restores the pre-repair mapping of the memory device in some examples. In some examples, an unused global column redundancy data path may be repurposed to provide repair information to the self-test circuit to implement the pre-repair mapping.
    Type: Application
    Filed: March 21, 2024
    Publication date: October 3, 2024
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: TAKAMASA SUZUKI, YASUSHI MATSUBARA, HARUTAKA MAKABE
  • Patent number: 11742250
    Abstract: Disclosed herein is an apparatus that includes a first semiconductor chip, and a first TSV penetrating the first semiconductor chip. The first semiconductor chip includes a first resistor coupled between a first power supply and a first node, a switch circuit coupled between the first node and the first TSV, a pad electrode operatively coupled to the first node, and a constant current source operatively coupled to either one of the first node and the pad electrode.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: August 29, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Harutaka Makabe
  • Publication number: 20220059418
    Abstract: Disclosed herein is an apparatus that includes a first semiconductor chip, and a first TSV penetrating the first semiconductor chip. The first semiconductor chip includes a first resistor coupled between a first power supply and a first node, a switch circuit coupled between the first node and the first TSV, a pad electrode operatively coupled to the first node, and a constant current source operatively coupled to either one of the first node and the pad electrode.
    Type: Application
    Filed: August 18, 2020
    Publication date: February 24, 2022
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Harutaka Makabe
  • Publication number: 20220028749
    Abstract: Disclosed herein is an apparatus that includes a first semiconductor chip, first and second TSVs penetrating the first semiconductor chip, a first path including the first TSV, a second path including the second TSV, a first charge circuit configured to charge the first path, a second charge circuit configured to charge the second path, a first discharge circuit configured to discharge the first path, a second discharge circuit configured to discharge the second path, and a comparator circuit configured to compare a potential of the first path with a potential of the second path.
    Type: Application
    Filed: September 29, 2021
    Publication date: January 27, 2022
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Harutaka Makabe
  • Patent number: 11164856
    Abstract: Disclosed herein is an apparatus that includes a first semiconductor chip, first and second TSVs penetrating the first semiconductor chip, a first path including the first TSV, a second path including the second TSV, a first charge circuit configured to charge the first path, a second charge circuit configured to charge the second path, a first discharge circuit configured to discharge the first path, a second discharge circuit configured to discharge the second path, and a comparator circuit configured to compare a potential of the first path with a potential of the second path.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: November 2, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Harutaka Makabe
  • Publication number: 20210091058
    Abstract: Disclosed herein is an apparatus that includes a first semiconductor chip, first and second TSVs penetrating the first semiconductor chip, a first path including the first TSV, a second path including the second TSV, a first charge circuit configured to charge the first path, a second charge circuit configured to charge the second path, a first discharge circuit configured to discharge the first path, a second discharge circuit configured to discharge the second path, and a comparator circuit configured to compare a potential of the first path with a potential of the second path.
    Type: Application
    Filed: September 19, 2019
    Publication date: March 25, 2021
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Harutaka Makabe