Patents by Inventor Haruto Nagata

Haruto Nagata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080308927
    Abstract: A semiconductor chip is mounted on an upper surface of the heat sink plate that is provided with a plurality of heat releasing terminals on a lower surface of the heat releasing. A plurality of electric signal terminals are regularly disposed in a lattice-like manner around the heat sink plate. Lower end surfaces of the electric signal terminals and the heat releasing terminals are exposed from and sealed with a sealing resin. The heat sink plate is formed as an integrated body including a protruding portion that protrudes from a central portion of an upper surface and supports the semiconductor chip, a plurality of supporting portions that are positioned around a rear surface of the protruding portion so as to support the protruding portion and that are exposed at a rear surface of the sealing resin, the plurality of heat releasing terminals, and a thin-walled portion that is recessed from lower end surfaces of the supporting portions and the heat releasing terminals.
    Type: Application
    Filed: May 14, 2008
    Publication date: December 18, 2008
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Haruto Nagata, Masanori Minamio, Hiroshi Horiki
  • Patent number: 7247509
    Abstract: A solid-state imaging device is manufactured according to the steps below. A lattice-shaped rib forming member, which is an aggregation of a plurality of frame-shaped ribs for configuring a plurality of solid-state imaging devices, is resin-molded. An aggregate wiring board is used, which has regions corresponding to a plurality of the wiring boards, and in which a plurality of the wiring members are provided in each of the regions, and the imaging element is fastened to each region of the aggregate wiring board and the electrodes of the imaging elements and the wiring members are connected by a thin metal wire. The rib forming member is placed on the wiring board face and joined to the wiring board face, so that the imaging element is disposed inside the lattice elements of the rib forming member.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: July 24, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kouichi Yamauchi, Masanori Minamio, Katsutoshi Shimizu, Haruto Nagata
  • Publication number: 20070007633
    Abstract: A resin-encapsulated semiconductor device includes: a semiconductor chip on a surface of which a group of electrodes is disposed; a plurality of inner leads arranged along a periphery of the semiconductor chip; connecting members for connecting the electrodes of the semiconductor chip with the respective inner leads, an encapsulating resin for encapsulating surfaces of the semiconductor chip and the connecting members; and external electrodes exposed from the encapsulating resin. Each of the inner leads extends across the periphery of the semiconductor chip from an internal side to an external side of the periphery, and includes a protruded portion provided on a surface of the inner lead on an external side relative to the periphery of the semiconductor chip, the protruded portion being protruded in a thickness direction.
    Type: Application
    Filed: September 15, 2006
    Publication date: January 11, 2007
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Masanori Minamio, Haruto Nagata, Tetsushi Nishio
  • Patent number: 7126209
    Abstract: A resin-encapsulated semiconductor device includes: a semiconductor chip on a surface of which a group of electrodes is disposed; a plurality of inner leads arranged along a periphery of the semiconductor chip; connecting members for connecting the electrodes of the semiconductor chip with the respective inner leads, an encapsulating resin for encapsulating surfaces of the semiconductor chip and the connecting members; and external electrodes exposed from the encapsulating resin. Each of the inner leads extends across the periphery of the semiconductor chip from an internal side to an external side of the periphery, and includes a protruded portion provided on a surface of the inner lead on an external side relative to the periphery of the semiconductor chip, the protruded portion being protruded in a thickness direction.
    Type: Grant
    Filed: December 21, 2004
    Date of Patent: October 24, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masanori Minamio, Haruto Nagata, Tetsushi Nishio
  • Publication number: 20050151242
    Abstract: A semiconductor chip is mounted on an upper surface of the heat sink plate that is provided with a plurality of heat releasing terminals on a lower surface of the heat releasing. A plurality of electric signal terminals are regularly disposed in a lattice-like manner around the heat sink plate. Lower end surfaces of the electric signal terminals and the heat releasing terminals are exposed from and sealed with a sealing resin. The heat sink plate is formed as an integrated body including a protruding portion that protrudes from a central portion of an upper surface and supports the semiconductor chip, a plurality of supporting portions that are positioned around a rear surface of the protruding portion so as to support the protruding portion and that are exposed at a rear surface of the sealing resin, the plurality of heat releasing terminals, and a thin-walled portion that is recessed from lower end surfaces of the supporting portions and the heat releasing terminals.
    Type: Application
    Filed: January 5, 2005
    Publication date: July 14, 2005
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Haruto Nagata, Masanori Minamio, Hiroshi Horiki
  • Publication number: 20050110121
    Abstract: A resin-encapsulated semiconductor device includes: a semiconductor chip on a surface of which a group of electrodes is disposed; a plurality of inner leads arranged along a periphery of the semiconductor chip; connecting members for connecting the electrodes of the semiconductor chip with the respective inner leads, an encapsulating resin for encapsulating surfaces of the semiconductor chip and the connecting members; and external electrodes exposed from the encapsulating resin. Each of the inner leads extends across the periphery of the semiconductor chip from an internal side to an external side of the periphery, and includes a protruded portion provided on a surface of the inner lead on an external side relative to the periphery of the semiconductor chip, the protruded portion being protruded in a thickness direction.
    Type: Application
    Filed: December 21, 2004
    Publication date: May 26, 2005
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masanori Minamio, Haruto Nagata, Tetsushi Nishio
  • Publication number: 20050074912
    Abstract: A solid-state imaging device is manufactured according to the steps below. A lattice-shaped rib forming member, which is an aggregation of a plurality of frame-shaped ribs for configuring a plurality of solid-state imaging devices, is resin-molded. An aggregate wiring board is used, which has regions corresponding to a plurality of the wiring boards, and in which a plurality of the wiring members are provided in each of the regions, and the imaging element is fastened to each region of the aggregate wiring board and the electrodes of the imaging elements and the wiring members are connected by a thin metal wire. The rib forming member is placed on the wiring board face and joined to the wiring board face, so that the imaging element is disposed inside the lattice elements of the rib forming member.
    Type: Application
    Filed: August 27, 2004
    Publication date: April 7, 2005
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kouichi Yamauchi, Masanori Minamio, Katsutoshi Shimizu, Haruto Nagata
  • Patent number: 5743007
    Abstract: A method for mounting on integrated circuit having many leads with narrow pitches on the printed circuit board. In a method, a resist layer is formed between lands on the board, and solder paste is applied with a stencil to the lands so that the positions of the solder paste on the lands are staggered. Then, leads of the integrated circuit are positioned on the lands. Then, reflow soldering of the leads to the lands is performed with the solder paste in a nitrogen environment. In a different embodiment, each land includes a first portion and a second portion having a width narrower than the first portion, and the second portions are arranged staggeredly among the lands. Then, solder paste is applied to the first portions having the wider width. Then, reflow soldering of the leads to the lands is performed with the solder paste in a nitrogen environment. If solder including bismuth is used, reflow soldering can be performed in ambient environment.
    Type: Grant
    Filed: January 17, 1996
    Date of Patent: April 28, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroaki Onishi, Haruto Nagata, Masato Hirano, Kenichiro Suetsugu