Patents by Inventor Haruya Iwata
Haruya Iwata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11588475Abstract: A semiconductor integrated circuit includes a clock controller generating a clock; and a plurality of blocks that operate by using the clock. The clock controller performs statistical processing for the plurality of blocks, controls a frequency of the clock to a first frequency, changes the frequency of the clock from the first frequency to a second frequency, generates the clock of the second frequency after a time predicted by the statistical processing as a time for which the second frequency is to be continued elapses from a timing when the frequency of the clock is changed, and supplies the generated clock to the blocks. The clock controller generates a third frequency clock obtained by decimating down the second frequency from the first frequency according to a time for which the first and second frequencies are to be continued after the frequency of the clock is changed from the second frequency to the first frequency, and supplies the generated clock to the blocks.Type: GrantFiled: October 13, 2021Date of Patent: February 21, 2023Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: Haruya Iwata, Tatsuya Tokue, Sohei Kushida, Takayuki Mori, Satoshi Kamiya
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Publication number: 20220029612Abstract: A semiconductor integrated circuit includes a clock controller generating a clock; and a plurality of blocks that operate by using the clock. The clock controller performs statistical processing for the plurality of blocks, controls a frequency of the clock to a first frequency, changes the frequency of the clock from the first frequency to a second frequency, generates the clock of the second frequency after a time predicted by the statistical processing as a time for which the second frequency is to be continued elapses from a timing when the frequency of the clock is changed, and supplies the generated clock to the blocks. The clock controller generates a third frequency clock obtained by decimating down the second frequency from the first frequency according to a time for which the first and second frequencies are to be continued after the frequency of the clock is changed from the second frequency to the first frequency, and supplies the generated clock to the blocks.Type: ApplicationFiled: October 13, 2021Publication date: January 27, 2022Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: Haruya IWATA, Tatsuya TOKUE, Sohei KUSHIDA, Takayuki MORI, Satoshi KAMIYA
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Patent number: 11177798Abstract: According to one embodiment, there is provided a control method. The method includes controlling a frequency of a clock to a first frequency. The method includes changing the frequency of the clock from the first frequency to a second frequency lower than the first frequency. The method includes statically predicting a time for which the second frequency is to be continued. The method includes changing the frequency of the clock from the second frequency to the first frequency after the time for which the second frequency is to be continued elapses from a timing when the frequency of the clock is changed to the second frequency.Type: GrantFiled: August 11, 2020Date of Patent: November 16, 2021Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: Haruya Iwata, Tatsuya Tokue, Sohei Kushida, Takayuki Mori, Satoshi Kamiya
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Publication number: 20210091756Abstract: According to one embodiment, there is provided a control method. The method includes controlling a frequency of a clock to a first frequency. The method includes changing the frequency of the clock from the first frequency to a second frequency lower than the first frequency. The method includes statically predicting a time for which the second frequency is to be continued. The method includes changing the frequency of the clock from the second frequency to the first frequency after the time for which the second frequency is to be continued elapses from a timing when the frequency of the clock is changed to the second frequency.Type: ApplicationFiled: August 11, 2020Publication date: March 25, 2021Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: Haruya IWATA, Tatsuya TOKUE, Sohei KUSHIDA, Takayuki MORI, Satoshi KAMIYA
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Publication number: 20210089213Abstract: An information processing apparatus comprises a central processor, a volatile memory, a non-volatile memory, a backup line, and a controller. The volatile memory is configured in such a manner that data is input and output thereto and therefrom via a bus under control of the central processor. The non-volatile memory is configured in such a manner that data is input and output thereto and therefrom via the bus under control of the central processor. The backup line is provided between the volatile memory and the non-volatile memory. The controller is configured to control data transfer performed between the volatile memory and the non-volatile memory via the backup line in a transition period between a normal mode of supplying normal power to the volatile memory and a low power consumption mode of reducing or interrupting normal power to be supplied to the volatile memory.Type: ApplicationFiled: March 3, 2020Publication date: March 25, 2021Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: Sohei KUSHIDA, Tatsuya TOKUE, Haruya IWATA, Satoshi KAMIYA, Takayuki MORI
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Patent number: 10460772Abstract: According to one embodiment, there is provided a semiconductor device comprising: a control circuit connected to a bus; a first circuit operating under control of the control circuit; a bus access detection circuit that detects bus access from the control circuit to the first circuit without going through the bus; a switch element connected between the first circuit and a power supply; and a second circuit connected between the first circuit and the bus, the second circuit controlling, when the bus access to the first circuit is detected by the bus access detection circuit, the switch element such that power from the power supply is supplied to the first circuit.Type: GrantFiled: September 11, 2018Date of Patent: October 29, 2019Assignees: KABUSHIKI KAISHA TOSHIBA, Toshiba Electronic Devices & Storage CorporationInventors: Takayuki Mori, Tatsuya Tokue, Haruya Iwata, Sohei Kushida, Satoshi Kamiya
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Publication number: 20190287577Abstract: According to one embodiment, there is provided a semiconductor device comprising: a control circuit connected to a bus; a first circuit operating under control of the control circuit; a bus access detection circuit that detects bus access from the control circuit to the first circuit without going through the bus; a switch element connected between the first circuit and a power supply; and a second circuit connected between the first circuit and the bus, the second circuit controlling, when the bus access to the first circuit is detected by the bus access detection circuit, the switch element such that power from the power supply is supplied to the first circuit.Type: ApplicationFiled: September 11, 2018Publication date: September 19, 2019Applicants: KABUSHIKI KAISHA TOSHIBA, Toshiba Electronic Devices & Storage CorporationInventors: Takayuki MORI, Tatsuya TOKUE, Haruya IWATA, Sohei KUSHIDA, Satoshi KAMIYA
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Patent number: 6798839Abstract: Coded image data having a DTS (decode time stamp) appended for each frame are written into an input buffer. A portion of the storage area of the input buffer is scanned to produce identification information (ID) for each frame of image data. For each frame of image data, the ID, DTS, storage location in the buffer and coding type are held in the form of a mapping table. The system time clock (STC) is compared with the DTSs in the table. When a match occurs, the storage location for the corresponding frame of image data is read from the table and sent to a decoder, which in turn reads the corresponding image data from the buffer and decodes it.Type: GrantFiled: December 11, 2001Date of Patent: September 28, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Haruya Iwata, Naoyuki Kai
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Patent number: 6738525Abstract: The variable length code tables 10 are categorized into the first and second table groups, and a set of the entire bits of reference data consisting of variable length codes and part of bits of the table designation data for designating a table to which the reference data is referred, are inputted to the first table group, whereas a set of part of the bits of the reference data and the entire bits of the table designation data are inputted to the second table groups. Then, an output of either one of the first and second tables is selected by a selector of 2:1, and thus variable length decode data is obtained.Type: GrantFiled: August 30, 2000Date of Patent: May 18, 2004Assignee: Kabushiki Kaisha ToshibaInventor: Haruya Iwata
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Publication number: 20020071056Abstract: Coded image data having a DTS (decode time stamp) appended for each frame are written into an input buffer. A portion of the storage area of the input buffer is scanned to produce identification information (ID) for each frame of image data. For each frame of image data, the ID, DTS, storage location in the buffer and coding type are held in the form of a mapping table. The system time clock (STC) is compared with the DTSs in the table. When a match occurs, the storage location for the corresponding frame of image data is read from the table and sent to a decoder, which in turn reads the corresponding image data from the buffer and decodes it.Type: ApplicationFiled: December 11, 2001Publication date: June 13, 2002Inventors: Haruya Iwata, Naoyuki Kai