Patents by Inventor Haruyoshi Katagiri

Haruyoshi Katagiri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Metal sealed wafer level CSP
    Patent number: 7932602
    Abstract: A semiconductor device comprising: (a) a semiconductor substrate having a dicing region circumscribing a chip region, the chip region including a central region and a peripheral region around the central region; (b) an active electrical structure formed to extend from a first main surface to a second surface vertically spaced apart from the last main surface in the central region of the semiconductor substrate; (c) a through dummy isolation structure formed within the peripheral region to extend from the first main surface of the semiconductor substrate to a third surface vertically spaced apart from the first main surface of the semiconductor substrate, the through dummy isolation structure surrounding the active electrical structure; (d) an insulating layer disbursed throughout the active electrical structure within the central region and around the through dummy isolation structure of the peripheral region, the insulating layer including top and opposed peripheral sides; and (e) a metal film located over t
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: April 26, 2011
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Haruyoshi Katagiri
  • SEMICONDUCTOR DEVICE
    Publication number: 20090039471
    Abstract: A semiconductor device comprising: (a) a semiconductor substrate having a dicing region circumscribing a chip region, the chip region including a central region and a peripheral region around the central region; (b) an active electrical structure formed to extend from a first main surface to a second surface vertically spaced apart from the first main surface in the central region of the semiconductor substrate; (c) a through dummy isolation structure formed within the peripheral region to extend from the first main surface of the semiconductor substrate to a third surface vertically spaced apart from the first main surface of the semiconductor substrate, the through dummy isolation structure surrounding the active electrical structure; (d) an insulating layer disbursed throughout the active electrical structure within the central region and around the through dummy isolation structure of the peripheral region, the insulating layer including top and opposed peripheral sides; and (e) a metal film located over
    Type: Application
    Filed: June 27, 2008
    Publication date: February 12, 2009
    Inventor: Haruyoshi Katagiri