Patents by Inventor Haruyoshi Mori

Haruyoshi Mori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230352253
    Abstract: An AC switch that includes a semiconductor switch and a snubber circuit connected in parallel between a first terminal connected to an AC power supply via a circuit breaker and a second terminal connected to a load. The power converter is connected between a power storage device and the second terminal. The current detector detects a current flowing through the AC switch. When the AC power supply is normal, the controller turns on the semiconductor switch. When an open state of the circuit breaker is detected, the controller controls the power converter to supply a current having a phase opposite to that of the current detected by the current detector to flow through the semiconductor switch and supply the AC power to the load. The controller further turns off the semiconductor switch in response to that the amplitude of the current detected by the current detector is 0.
    Type: Application
    Filed: May 14, 2021
    Publication date: November 2, 2023
    Applicant: TOSHIBA MITSUBISHI-ELECTRIC INDUSTRIAL SYSTEMS CORPORATION
    Inventors: Yousuke HAYASHI, Xiaochen ZHANG, Haruyoshi MORI
  • Patent number: 5903181
    Abstract: A voltage-controlled transistor drive circuit includes a gate-voltage generating circuit for outputting on and off gate signal voltages in response to an input signal, switching a voltage-controlled transistor by applying the gate voltage to the gate of the voltage-controlled transistor; and a current limiting circuit limiting current flowing from the gate of the voltage-controlled transistor to the gate-voltage generating circuit when the gate-voltage generating circuit outputs an off gate signal voltage.
    Type: Grant
    Filed: November 25, 1996
    Date of Patent: May 11, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Haruyoshi Mori
  • Patent number: 5808504
    Abstract: The cutoff process of a collector current of an insulated gate transistor is divided into an emitter-to-collector voltage recovery period and a collector current cutoff period. During the emitter-to-collector voltage recovery period the resistance of a gate resistor of the transistor is reduced, and during the collector current cutoff period the resistance of the gate resistor is increased. With this arrangement, the cutoff time is shortened, thereby reducing switching loss and suppressing surge voltage.
    Type: Grant
    Filed: August 14, 1996
    Date of Patent: September 15, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Satoru Chikai, Haruyoshi Mori, Tomohiro Kobayashi
  • Patent number: 5166541
    Abstract: A switching apparatus including a plurality of semiconductor switching elements each of which has a pair of main circuit electrodes and a control electrode. Each load-side electrode of the pair of main circuit electrodes of each semiconductor switching element is connected in common and the control electrodes are controlled by a common control power supply so as to control the conductance between the main circuit electrodes. A transformer having a first coil and a second coil of the same polarity as the first coil is connected to each of the semiconductor switching elements. The first coil is inserted between the control signal source and the load-side main circuit electrode, and the second coil is inserted between the control signal source and the control electrode.
    Type: Grant
    Filed: July 24, 1991
    Date of Patent: November 24, 1992
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Haruyoshi Mori
  • Patent number: 4985819
    Abstract: An inverter apparatus having a reactor which suppresses ripple components contained in a charging current for a battery and is saturated when a current having a value larger than a predetermined value flows therethrough to have a very small inductance and allowing a small size and a low cost thereof to be designed.
    Type: Grant
    Filed: October 18, 1989
    Date of Patent: January 15, 1991
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Haruyoshi Mori, Nobuo Sashida
  • Patent number: 4922365
    Abstract: Disclosed is an overvoltage suppressing circuit for a semiconductor device connected between the poles of a DC power source and adapted to effect a switching operation. The circuit comprises: a serial circuit connected in parallel with a semiconductor device and including an overvoltage suppressing capacitor, an oscillation suppressing diode, and an impedance regulator connected in series each other, the impedance regulator being operable to change into a state of high impedance for suppressing a reverse current flowing into the oscillation suppressing diode when the oscillation suppressing diode is turned off; and a discharging device connected between a DC power source and the overvoltage suppressing capacitor for discharging to the DC power source a charge accumulated in the overvoltage suppressing capacitor when the oscillation suppressing diode is off.
    Type: Grant
    Filed: April 13, 1989
    Date of Patent: May 1, 1990
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Haruyoshi Mori
  • Patent number: 4775803
    Abstract: The invention relates to technology to minimize power for suppressing ON base current to a transistor. In a base drive circuit of transistor, current is supplied to base of first and second transistors connected in series to DC power source, and the transistors are rendered on or off.
    Type: Grant
    Filed: April 13, 1987
    Date of Patent: October 4, 1988
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Haruyoshi Mori