Patents by Inventor Haruyoshi YONEKAWA

Haruyoshi YONEKAWA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230243950
    Abstract: An apparatus and a method for performing azimuth angle estimation are realized in which an object region or only an object region of a specific type is used as an azimuth angle estimation target region. There are provided: an azimuth angle estimation region selection unit configured to be inputted with a speed-range map indicating a distance and a relative speed of an object having reflected a radar wave, and select an azimuth angle estimation target region from the inputted speed-range map; and an azimuth angle estimation unit configured to execute azimuth angle estimation for only a selected region. The azimuth angle estimation region selection unit detects, from the speed-range map, a cluster that is an aggregate of bright spots and satisfies a predetermined condition, and selects the detected cluster as the azimuth angle estimation target region.
    Type: Application
    Filed: April 14, 2021
    Publication date: August 3, 2023
    Inventor: HARUYOSHI YONEKAWA
  • Publication number: 20220172484
    Abstract: The present technology relates to an information processing method, a program, and an information processing apparatus capable of analyzing a learning situation of a model using a neural network. In step S1, feature data that numerically represents a feature of a feature map generated from input data in a model using a neural network is generated. In step S2, analysis data based on the feature data of a plurality of the feature maps is generated. The present technology can be applied to, for example, a system that recognizes a vehicle in front of a vehicle.
    Type: Application
    Filed: March 17, 2020
    Publication date: June 2, 2022
    Applicant: Sony Semiconductor Solutions Corporation
    Inventor: Haruyoshi Yonekawa
  • Publication number: 20200005131
    Abstract: A binarized neural network circuit includes: an input part configured to allow input of input values (binary) and weights; an XNOR gate circuit configured to receive the input values and the weights and take XNOR logic; a multibit bias input part configured to allow input of a multibit bias; a sum circuit part configured to sum each of XNOR logical values and the multibit bias; and an activation circuit part configured to output only a sign bit of a multibit signal generated by using the sum.
    Type: Application
    Filed: November 28, 2017
    Publication date: January 2, 2020
    Inventors: Hiroki NAKAHARA, Haruyoshi YONEKAWA