Abstract: According to one embodiment, a semiconductor memory device includes, on a substrate, a memory region and a peripheral circuit region in which an MOS transistor is formed. The MOS transistor includes a drain region and a source region disposed in a first direction parallel to a surface of the substrate. On a surface of the drain region, a drain electrode is formed to be connected with a contact plug. Further, on a surface of the source region, a source electrode is formed to be connected with a contact plug. When viewed in the first direction, the drain electrode has a region that does not overlap with the source electrode, and the source electrode has a region that does not overlap with the drain electrode.

Abstract: A semiconductor storage device includes a memory cell array and a peripheral circuit disposed at least partially below the memory cell array. The peripheral circuit includes an RC circuit in which a resistive portion and a capacitive portion are electrically connected to each other in series. The resistive portion includes first and second lower conductors at a level that is below the memory cell array, an upper conductor at a level that is above the memory cell array, a first contact that connects the first lower conductor to the upper conductor, and a second contact that connects the upper conductor to the second lower conductor. The first lower conductor, the first contact, the upper conductor, the second contact, and the second lower conductor are electrically connected in series in this order and the first lower conductor is closest to the capacitive portion.

Abstract: According to one embodiment, a semiconductor memory device includes, on a substrate, a memory region 600 and a peripheral circuit region 500 in which an MOS transistor 100 is formed. The MOS transistor 100 includes a drain region 120 and a source region 130 disposed in a first direction parallel to a surface of the substrate. On a surface of the drain region 120, a drain electrode 121 is formed to be connected with a contact plug 122. Further, on a surface of the source region 130, a source electrode 131 is formed to be connected with a contact plug 132. When viewed in the first direction, the drain electrode 121 has a region that does not overlap with the source electrode 131, and the source electrode 131 has a region that does not overlap with the drain electrode 121.

Abstract: Adverse effects when a carrier is open, such as particles adhesion to the substrate or natural oxidation film deposits on the substrate, as well as a rise in oxygen concentration and contamination of the substrate transfer chamber are prevented. Semiconductor manufacturing apparatus includes a carrier in which a cover unit is provided on a substrate loading/unloading opening for loading and unloading a substrate, a carrier open/close chamber continuously arranged to the carrier, a substrate transfer chamber continuously arranged to the carrier open/close chamber, a substrate processing chamber continuously arranged to the substrate transfer chamber, an exhaust means for exhausting the atmosphere in the carrier open/close chamber by suction, and an exhaust quantity adjuster means for adjusting the suction exhaust quantity of the exhaust means.

Abstract: Adverse effects when a carrier is open, such as particles adhesion to the substrate or natural oxidation film deposits on the substrate, as well as a rise in oxygen concentration and contamination of the substrate transfer chamber are prevented. Semiconductor manufacturing apparatus includes a carrier in which a cover unit is provided on a substrate loading/unloading opening for loading and unloading a substrate, a carrier open/close chamber continuously arranged to the carrier, a substrate transfer chamber continuously arranged to the carrier open/close chamber, a substrate processing chamber continuously arranged to the substrate transfer chamber, an exhaust means for exhausting the atmosphere in the carrier open/close chamber by suction, and an exhaust quantity adjuster means for adjusting the suction exhaust quantity of the exhaust means.

Abstract: Adverse effects when a carrier is open, such as particles adhesion to the substrate or natural oxidation film deposits on the substrate, as well as a rise in oxygen concentration and contamination of the substrate transfer chamber are prevented. Semiconductor manufacturing apparatus includes a carrier (10) in which a cover unit (10a) is provided on a substrate loading/unloading opening (10b) for loading and unloading a substrate (9), a carrier open/close chamber (61) continuously arranged to the carrier (10), a substrate transfer chamber (16) continuously arranged to the carrier open/close chamber, a substrate processing chamber continuously arranged to the substrate transfer chamber, an exhaust means (63) for exhausting the atmosphere in the carrier open/close chamber by suction, and an exhaust quantity adjuster means (65, 66) for adjusting the suction exhaust quantity of the exhaust means.

Abstract: First and second well regions of N conductivity type are formed in a P-type semiconductor substrate. A digital circuit is formed in the first well region. An analog circuit is formed in the second well region. A power source wiring for supplying a bias potential is connected to the substrate. The power source wiring is connected to a power source terminal which is different from the power source terminal of the digital circuit.

Abstract: In a semiconductor device having a digital circuit region and an analog circuit region formed on an N type semiconductor substrate, a P type well region is formed on the semiconductor substrate and between the digital circuit region and the analog circuit region. Furthermore, an N type first diffusion layer is formed on the well region. In the semiconductor device, the isolating portion formed between the digital and analog circuit regions not only shuts off an electrical noise between the regions but also absorbs an electrostatic surge input from an external device to a power source terminal, thereby protecting the digital and analog circuit regions from electrostatic breakdown.

Abstract: First and second well regions of a second conductivity type are formed in a semiconductor substrate of a first conductivity type. An analog circuit is formed in the first well region. A digital circuit is formed in the second well region.