Patents by Inventor Haruyuki NAKAGAWA

Haruyuki NAKAGAWA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11936999
    Abstract: Power consumption in realizing a convolutional neural network (CNN) is reduced. A solid-state imaging element according to the present technology includes a photoelectric conversion element that photoelectrically converts received light into signal charge corresponding to the amount of received light, a floating diffusion that holds the signal charge obtained by the photoelectric conversion element, a transfer control element that controls transfer of the signal charge from the photoelectric conversion element to the floating diffusion, and a control unit that controls application of a drive voltage to the transfer control element on the basis of a convolution coefficient in a CNN.
    Type: Grant
    Filed: October 13, 2020
    Date of Patent: March 19, 2024
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Haruyuki Nakagawa
  • Publication number: 20230154952
    Abstract: To enhance a charge transfer efficiency in a transfer gate having a vertical gate electrode. A solid-state imaging element includes a photoelectric conversion section, a charge accumulating section, and a transfer gate. The photoelectric conversion section is formed in a depth direction of a semiconductor substrate, and generates charges corresponding to a quantity of received light. The charge accumulating section accumulates the charges generated by the photoelectric conversion section. The transfer gate transfers the charges generated by the photoelectric conversion section to the charge accumulating section. The transfer gate includes a plurality of vertical gate electrodes which is filled to a predetermined depth from an interface of the semiconductor substrate, and at least a part of a diameter is different in the depth direction of the semiconductor substrate.
    Type: Application
    Filed: January 6, 2023
    Publication date: May 18, 2023
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Haruyuki NAKAGAWA
  • Patent number: 11587963
    Abstract: To enhance a charge transfer efficiency in a transfer gate having a vertical gate electrode. A solid-state imaging element includes a photoelectric conversion section, a charge accumulating section, and a transfer gate. The photoelectric conversion section is formed in a depth direction of a semiconductor substrate, and generates charges corresponding to a quantity of received light. The charge accumulating section accumulates the charges generated by the photoelectric conversion section. The transfer gate transfers the charges generated by the photoelectric conversion section to the charge accumulating section. The transfer gate includes a plurality of vertical gate electrodes which is filled to a predetermined depth from an interface of the semiconductor substrate, and at least a part of a diameter is different in the depth direction of the semiconductor substrate.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: February 21, 2023
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Haruyuki Nakagawa
  • Publication number: 20220400222
    Abstract: Power consumption in realizing a convolutional neural network (CNN) is reduced. A solid-state imaging element according to the present technology includes a photoelectric conversion element that photoelectrically converts received light into signal charge corresponding to the amount of received light, a floating diffusion that holds the signal charge obtained by the photoelectric conversion element, a transfer control element that controls transfer of the signal charge from the photoelectric conversion element to the floating diffusion, and a control unit that controls application of a drive voltage to the transfer control element on the basis of a convolution coefficient in a CNN.
    Type: Application
    Filed: October 13, 2020
    Publication date: December 15, 2022
    Applicant: Sony Semiconductor Solutions Corporation
    Inventor: Haruyuki NAKAGAWA
  • Patent number: 11502122
    Abstract: The present technology relates to an imaging element and an electronic device enabling suppression of generation of noise. Provided with a substrate, a first photoelectric conversion region provided on the substrate, a second photoelectric conversion region provided on the substrate and adjacent to the first photoelectric conversion region, a trench provided on the substrate and between the first photoelectric conversion region and the second photoelectric conversion region, a first impurity region including a first impurity provided on the substrate and on a sidewall of the trench, and a second impurity region including a second impurity provided on the substrate and between the first photoelectric conversion region or the second photoelectric conversion region and the first impurity region. The present technology can be applied to an imaging element.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: November 15, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Haruyuki Nakagawa
  • Publication number: 20220139992
    Abstract: There is provided an image sensor including a first substrate including a plurality of pixels and a plurality of vertical signal lines and a plurality of first wiring layers and a second substrate including a plurality of second wiring layers. The first and second substrates are secured together between the pluralities of first and second wiring layers. First pads are provided between one of the plurality of first wiring layers and one of the plurality of second wiring layers and second pads are provided between another of the plurality of first wiring layers and another of the plurality of second wiring layers. First vias and second vias connect the first pads and the one of the plurality of first wiring layers and the one of the plurality of second wiring layers together.
    Type: Application
    Filed: February 28, 2020
    Publication date: May 5, 2022
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Tomomi ITO, Kazuyoshi YAMASHITA, Atsushi MASAGAKI, Shinobu ASAYAMA, Shinya ITOH, Haruyuki NAKAGAWA, Kyohei MIZUTA, Susumu OOKI, Osamu OKA, Kazuto KAMIMURA, Takuji MATSUMOTO, Kenju NISHIKIDO
  • Publication number: 20210066358
    Abstract: The present technology relates to an imaging element and an electronic device enabling suppression of generation of noise. Provided with a substrate, a first photoelectric conversion region provided on the substrate, a second photoelectric conversion region provided on the substrate and adjacent to the first photoelectric conversion region, a trench provided on the substrate and between the first photoelectric conversion region and the second photoelectric conversion region, a first impurity region including a first impurity provided on the substrate and on a sidewall of the trench, and a second impurity region including a second impurity provided on the substrate and between the first photoelectric conversion region or the second photoelectric conversion region and the first impurity region. The present technology can be applied to an imaging element.
    Type: Application
    Filed: March 5, 2019
    Publication date: March 4, 2021
    Inventor: HARUYUKI NAKAGAWA
  • Publication number: 20200135781
    Abstract: To enhance a charge transfer efficiency in a transfer gate having a vertical gate electrode. A solid-state imaging element includes a photoelectric conversion section, a charge accumulating section, and a transfer gate. The photoelectric conversion section is formed in a depth direction of a semiconductor substrate, and generates charges corresponding to a quantity of received light. The charge accumulating section accumulates the charges generated by the photoelectric conversion section. The transfer gate transfers the charges generated by the photoelectric conversion section to the charge accumulating section. The transfer gate includes a plurality of vertical gate electrodes which is filled to a predetermined depth from an interface of the semiconductor substrate, and at least a part of a diameter is different in the depth direction of the semiconductor substrate.
    Type: Application
    Filed: February 13, 2018
    Publication date: April 30, 2020
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Haruyuki NAKAGAWA