Patents by Inventor Haruyuki Sorada
Haruyuki Sorada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110244645Abstract: A semiconductor device includes: a semiconductor substrate in which a trench is formed; a source region and a drain region each of which is buried in the trench and contains an impurity of the same conductive type; a semiconductor FIN buried in the trench and provided between the source and drain regions; a gate insulating film provided on a side surface of the semiconductor FIN as well as the upper surface of the semiconductor FIN; and a gate electrode formed on the gate insulating film.Type: ApplicationFiled: June 16, 2011Publication date: October 6, 2011Applicant: Panasonic CorporationInventors: Junko IWANAGA, Takeshi Takagi, Yoshihiko Kanzawa, Haruyuki Sorada, Tohru Saitoh, Takahiro Kawashima
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Patent number: 7986002Abstract: A semiconductor device includes: a semiconductor substrate in which a trench is formed; a source region and a drain region each of which is buried in the trench and contains an impurity of the same conductive type; a semiconductor FIN buried in the trench and provided between the source and drain regions; a gate insulating film provided on a side surface of the semiconductor FIN as well as the upper surface of the semiconductor FIN; and a gate electrode formed on the gate insulating film.Type: GrantFiled: March 19, 2004Date of Patent: July 26, 2011Assignee: Panasonic CorporationInventors: Junko Iwanaga, Takeshi Takagi, Yoshihiko Kanzawa, Haruyuki Sorada, Tohru Saitoh, Takahiro Kawashima
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Patent number: 7564073Abstract: A semiconductor integrated circuit fabrication method according to this invention includes: a step of forming a pair of first device forming regions and a pair of second device forming regions in a surface layer portion of a semiconductor substrate by surrounding each of the regions by device isolation; a step of forming a first oxide film covering the surface of the semiconductor substrate after the preceding step; a step of removing an intended portion of the first oxide film to expose the pair of second device forming regions; a step of forming a pair of heterojunction structures, by selective epitaxial growth, on the pair of second device forming regions thus exposed; a step of forming a second oxide film covering the surface of the substrate after the preceding step; and a step of forming a pair of gate electrodes above each of the pair of first device forming regions and the pair of second device forming regions, whereby a normal complementary MOS transistor and a heterojunction complementary MOS transiType: GrantFiled: December 6, 2005Date of Patent: July 21, 2009Assignee: Panasonic CorporationInventors: Haruyuki Sorada, Akira Asai, Takeshi Takagi, Akira Inoue, Yoshio Kawashima
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Patent number: 7554139Abstract: A production method for a semiconductor device according to the present invention includes: step (A) of providing a substrate including a semiconductor layer having a principal face, the substrate having a device isolation structure (STI) formed in an isolation region 70 for partitioning the principal face into a plurality of device active regions 50, 60; step (B) of growing an epitaxial layer containing Si and Ge on selected device active regions 50 among the plurality of device active regions 50, 60 of the principal face of the semiconductor layer; and step (C) of forming a transistor in, among the plurality of device active regions 50, 60, each of the device active regions 50 on which the epitaxial layer is formed and each of the device active regions A2 on which the epitaxial layer is not formed.Type: GrantFiled: April 11, 2005Date of Patent: June 30, 2009Assignee: Panasonic CorporationInventors: Akira Inoue, Haruyuki Sorada, Yoshio Kawashima, Takeshi Takagi
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Patent number: 7473967Abstract: A semiconductor device according to this invention includes: a first insulating layer (11); a first body section (13) including an island-shaped semiconductor formed on the first insulating layer; a second body section (14) including an island-shaped semiconductor formed on the first insulating layer; a ridge-shaped connecting section (15) formed on the first insulating layer to interconnect the first body section and the second body section; a channel region (15a) formed by at least a part of the connecting section in lengthwise direction of the connecting section; a gate electrode (18) formed to cover a periphery of the channel region, with a second insulating layer intervening therebetween; a source region formed to extend over the first body section and a portion of the connecting section between the first body section and the channel region; and a drain region formed to extend over the second body section and a portion of the connecting section between the second body section and the channel region, wherType: GrantFiled: May 31, 2004Date of Patent: January 6, 2009Assignee: Panasonic CorporationInventors: Haruyuki Sorada, Takeshi Takagi, Akira Asai, Yoshihiko Kanzawa, Kouji Katayama, Junko Iwanaga
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Publication number: 20080135877Abstract: A production method for a semiconductor device according to the present invention includes: step (A) of providing a substrate including a semiconductor layer having a principal face, the substrate having a device isolation structure (STI) formed in an isolation region 70 for partitioning the principal face into a plurality of device active regions 50, 60; step (B) of growing an epitaxial layer containing Si and Ge on selected device active regions 50 among the plurality of device active regions 50, 60 of the principal face of the semiconductor layer; and step (C) of forming a transistor in, among the plurality of device active regions 50, 60, each of the device active regions 50 on which the epitaxial layer is formed and each of the device active regions A2 on which the epitaxial layer is not formed.Type: ApplicationFiled: April 11, 2005Publication date: June 12, 2008Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO,. LTD.Inventors: Akira Inoue, Haruyuki Sorada, Yoshio Kawashima, Takeshi Takagi
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Patent number: 7235830Abstract: The present invention provides a semiconductor device comprising: a semiconductor layer (3); a gate electrode (11) formed on the semiconductor layer (3) via a gate insulation film (10); and a first insulation film (13) formed at one or more of sidewalls of the semiconductor layer (3), the gate insulation film (10) and the gate electrode (11); wherein the first insulation film (13) overlies a part of the gate insulation film (10) surface. According to the semiconductor device, leakage current at the isolation edge can be suppressed and thus reliability can be improved.Type: GrantFiled: October 28, 2005Date of Patent: June 26, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Haruyuki Sorada, Takeshi Takagi, Akira Asai, Akira Inoue
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Publication number: 20070108514Abstract: A semiconductor device according to the present invention, which comprises a MISFET, has a semiconductor layer (3) having a recessed portion (101) formed in the surface thereof, the recessed portion (101) having an opening the outer circumference of which is closed, a gate insulating film (13) formed so as to cover at least the inner face of the recessed portion (3), a gate electrode (14) filling the recessed portion (101) such that the gate insulating film (13) is interposed between the gate electrode (14) and the inner face of the recessed portion (101), and a pair of source/drains (102), located on both sides of the gate electrode (14) when viewed in plan and formed to a predetermined depth from the surface of the semiconductor layer (3).Type: ApplicationFiled: April 28, 2004Publication date: May 17, 2007Inventors: Akira Inoue, Takeshi Takagi, Haruyuki Sorada
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Publication number: 20070052041Abstract: A semiconductor device according to this invention includes: a first insulating layer (11); a first body section (13) including an island-shaped semiconductor formed on the first insulating layer; a second body section (14) including an island-shaped semiconductor formed on the first insulating layer; a ridge-shaped connecting section (15) formed on the first insulating layer to interconnect the first body section and the second body section; a channel region (15a) formed by at least a part of the connecting section in lengthwise direction of the connecting section; a gate electrode (18) formed to cover a periphery of the channel region, with a second insulating layer intervening therebetween; a source region formed to extend over the first body section and a portion of the connecting section between the first body section and the channel region; and a drain region formed to extend over the second body section and a portion of the connecting section between the second body section and the channel region, wherType: ApplicationFiled: May 31, 2004Publication date: March 8, 2007Inventors: Haruyuki Sorada, Takeshi Takagi, Akira Asai, Yoshihiko Kanzawa, Kouji Katayama, Junko Iwanaga
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Patent number: 7145168Abstract: On an Si substrate 1, a buffer layer 2, a SiGe layer 3, and an Si cap layer 4 are formed. A mask is formed on the substrate, and then the substrate is patterned. In this manner, a trench 7a is formed so as to reach the Si substrate 1 and have the side faces of the SiGe layer 3 exposed. Then, the surface of the trench 7a is subjected to heat treatment for one hour at 750° C. so that Ge contained in a surface portion of the SiGe layer 3 is evaporated. Thus, a Ge evaporated portion 8 having a lower Ge content than that of other part of the SiGe layer 3 is formed in part of the SiGe layer 3 exposed at part of the trench 7a. Thereafter, the walls of the trench 7a are oxidized.Type: GrantFiled: November 24, 2004Date of Patent: December 5, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshihiro Hara, Akira Asai, Gaku Sugahara, Haruyuki Sorada, Teruhito Ohnishi
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Patent number: 7126170Abstract: A MISFET according to this invention includes: a substrate having a semiconductor layer; an active region formed in the semiconductor layer; a gate insulator formed on the active region; a gate formed on the gate insulator; and a source region and a drain region, wherein: the active region is formed, in plan view, to have a body portion and a projecting portion projecting from a periphery of the body portion; the gate is formed, in plan view, to intersect the body portion of the active region, cover a pair of connecting portions connecting a periphery of the projecting portion to the periphery of the body portion and allow a part of the projecting portion to project from a periphery of the gate; and the source region and the drain region are formed in regions of the body portion of the active region which are situated on opposite sides of the gate in plan view, respectively.Type: GrantFiled: November 2, 2004Date of Patent: October 24, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Akira Inoue, Takeshi Takagi, Akira Asai, Haruyuki Sorada
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Patent number: 7119417Abstract: A semiconductor device of this invention includes: a semiconductor substrate; a gate electrode formed on the semiconductor substrate; a pair of source and drain electrodes respectively formed in regions of the semiconductor substrate situated on opposite sides of the gate electrode in a plan view; and a germanium-containing channel layer situated below the gate electrode to sandwich an gate insulator therebetween and intervening between the pair of source and drain electrodes, wherein a silicide layer forming at least a part of the source and drain electrodes has a lower germanium concentration than the channel layer.Type: GrantFiled: September 24, 2004Date of Patent: October 10, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Haruyuki Sorada, Takeshi Takagi, Akira Inoue, Yoshio Kawashima
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Publication number: 20060208300Abstract: A semiconductor device includes: a semiconductor substrate in which a trench is formed; a source region and a drain region each of which is buried in the trench and contains an impurity of the same conductive type; a semiconductor FIN buried in the trench and provided between the source and drain regions; a gate insulating film provided on a side surface of the semiconductor FIN as well as the upper surface of the semiconductor FIN; and a gate electrode formed on the gate insulating film.Type: ApplicationFiled: March 19, 2004Publication date: September 21, 2006Inventors: Junko Iwanaga, Takeshi Takagi, Yoshihiko Kanzawa, Haruyuki Sorada, Tohru Saitoh, Takahiro Kawashima
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Patent number: 7087473Abstract: A semiconductor integrated circuit fabrication method according to this invention includes: a step of forming a pair of first device forming regions and a pair of second device forming regions in a surface layer portion of a semiconductor substrate by surrounding each of the regions by device isolation; a step of forming a first oxide film covering the surface of the semiconductor substrate after the preceding step; a step of removing an intended portion of the first oxide film to expose the pair of second device forming regions; a step of forming a pair of heterojunction structures, by selective epitaxial growth, on the pair of second device forming regions thus exposed; a step of forming a second oxide film covering the surface of the substrate after the preceding step; and a step of forming a pair of gate electrodes above each of the pair of first device forming regions and the pair of second device forming regions, whereby a normal complementary MOS transistor and a heterojunction complementary MOS transiType: GrantFiled: June 14, 2004Date of Patent: August 8, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Haruyuki Sorada, Akira Asai, Takeshi Takagi, Akira Inoue, Yoshio Kawashima
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Publication number: 20060086988Abstract: A semiconductor integrated circuit fabrication method according to this invention includes: a step of forming a pair of first device forming regions and a pair of second device forming regions in a surface layer portion of a semiconductor substrate by surrounding each of the regions by device isolation; a step of forming a first oxide film covering the surface of the semiconductor substrate after the preceding step; a step of removing an intended portion of the first oxide film to expose the pair of second device forming regions; a step of forming a pair of heterojunction structures, by selective epitaxial growth, on the pair of second device forming regions thus exposed; a step of forming a second oxide film covering the surface of the substrate after the preceding step; and a step of forming a pair of gate electrodes above each of the pair of first device forming regions and the pair of second device forming regions, whereby a normal complementary MOS transistor and a heterojunction complementary MOS transiType: ApplicationFiled: December 6, 2005Publication date: April 27, 2006Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Haruyuki Sorada, Akira Asai, Takeshi Takagi, Akira Inoue, Yoshio Kawashima
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Publication number: 20060054944Abstract: The present invention provides a semiconductor device comprising: a semiconductor layer (3); a gate electrode (11) formed on the semiconductor layer (3) via a gate insulation film (10); and a first insulation film (13) formed at one or more of sidewalls of the semiconductor layer (3), the gate insulation film (10) and the gate electrode (11); wherein the first insulation film (13) overlies a part of the gate insulation film (10) surface. According to the semiconductor device, leakage current at the isolation edge can be suppressed and thus reliability can be improved.Type: ApplicationFiled: October 28, 2005Publication date: March 16, 2006Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Haruyuki Sorada, Takeshi Takagi, Akira Asai, Akira Inoue
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Patent number: 6987065Abstract: The present invention provides a semiconductor device comprising: a semiconductor layer (3); a gate electrode (11) formed on the semiconductor layer (3) via a gate insulation film (10); and a first insulation film (13) formed at one or more of sidewalls of the semiconductor layer (3), the gate insulation film (10) and the gate electrode (11); wherein the first insulation film (13) overlies a part of the gate insulation film (10) surface. According to the semiconductor device, leakage current at the isolation edge can be suppressed and thus reliability can be improved.Type: GrantFiled: July 15, 2004Date of Patent: January 17, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Haruyuki Sorada, Takeshi Takagi, Akira Asai, Akira Inoue
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Patent number: 6917075Abstract: A semiconductor device and a method of fabricating the same according to this invention are such that: a gate insulator is formed over a predetermined region of a semiconductor substrate; a gate electrode is formed on the gate insulator; source and drain regions respectively formed in portions of the predetermined region that are situated on both sides of the gate electrode in plan view; a body region formed by a region of the predetermined region exclusive of the source and drain regions; and a contact electrically interconnecting the gate electrode and the body region, wherein a portion of the contact which is connected to the gate electrode is formed to intersect the gate electrode in plan view.Type: GrantFiled: January 7, 2004Date of Patent: July 12, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Akira Inoue, Akira Asai, Teruhito Ohnishi, Haruyuki Sorada, Yoshihiro Hara, Takeshi Takagi
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Publication number: 20050133834Abstract: A semiconductor device of this invention includes: a semiconductor substrate; a gate electrode formed on the semiconductor substrate; a pair of source and drain electrodes respectively formed in regions of the semiconductor substrate situated on opposite sides of the gate electrode in a plan view; and a germanium-containing channel layer situated below the gate electrode to sandwich an gate insulator therebetween and intervening between the pair of source and drain electrodes, wherein a silicide layer forming at least a part of the source and drain electrodes has a lower germanium concentration than the channel layer.Type: ApplicationFiled: September 24, 2004Publication date: June 23, 2005Inventors: Haruyuki Sorada, Takeshi Takagi, Akira Inoue, Yoshio Kawashima
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Publication number: 20050087803Abstract: On an Si substrate 1, a buffer layer 2, a SiGe layer 3, and an Si cap layer 4 are formed. A mask is formed on the substrate, and then the substrate is patterned. In this manner, a trench 7a is formed so as to reach the Si substrate 1 and have the side faces of the SiGe layer 3 exposed. Then, the surface of the trench 7a is subjected to heat treatment for one hour at 750° C. so that Ge contained in a surface portion of the SiGe layer 3 is evaporated. Thus, a Ge evaporated portion 8 having a lower Ge content than that of other part of the SiGe layer 3 is formed in part of the SiGe layer 3 exposed at part of the trench 7a. Thereafter, the walls of the trench 7a are oxidized.Type: ApplicationFiled: November 24, 2004Publication date: April 28, 2005Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshihiro Hara, Akira Asai, Gaku Sugahara, Haruyuki Sorada, Teruhito Ohnishi