Abstract: A memory configuration (20) which includes a first and second bank (B0, B1). Both bank arrays comprises a plurality of wordlines (WLs) and bitlines (BLs). The memory configuration further includes a plurality of column decoder circuits (CDEC0-CDEC7), and a plurality of y-select conductors (C0-C15) generally parallel to the plurality of bitlines of the first bank array. Each of the plurality of y-select conductors is operable to be selected by one of the plurality of column decoder circuits in response to a column address. The memory configuration further includes a plurality of column factor conductors (F0.sub.I, F1.sub.I, F2.sub.I) formed in a direct periphery area existing between the first and second bank arrays. Still further, the memory configuration includes a power conductor (PDD.sub.I) formed between the first and second bank arrays, and aligned generally parallel to the plurality of wordlines of the first and second bank arrays.