Abstract: A silicon carrier space transformer assembly includes one or more silicon structures, which provide space transformer scaling to permit interconnection for fine pitch input/output interconnections with a semiconductor die or wafer, and fine pitch test probe tips connected to the one or more silicon structures.

Abstract: A silicon carrier space transformer assembly includes one or more silicon structures, which provide space transformer scaling to permit interconnection for fine pitch input/output interconnections with a semiconductor die or wafer, and fine pitch test probe tips connected to the one or more silicon structures.

Abstract: A silicon carrier space transformer assembly includes one or more silicon structures, which provide space transformer scaling to permit interconnection for fine pitch input/output interconnections with a semiconductor die or wafer, and fine pitch test probe tips connected to the one or more silicon structures.

Abstract: A silicon carrier space transformer assembly includes one or more silicon structures, which provide space transformer scaling to permit interconnection for fine pitch input/output interconnections with a semiconductor die or wafer, and fine pitch test probe tips connected to the one or more silicon structures.

Abstract: A tamper resistant, integrated circuit (IC) module includes a ceramic-based chip carrier, one or more integrated circuit chips attached to the chip carrier, and a cap structure attached to the chip carrier, covering the one or more integrated circuit chips. A conductive grid structure is formed in the chip carrier and cap structure, the conductive structure having a plurality of meandering lines disposed in an x-direction, a y-direction, and a z-direction. The conductive grid structure is configured so as to detect an attempt to penetrate the IC module.

Abstract: A tamper resistant, integrated circuit (IC) module includes a ceramic-based chip carrier, one or more integrated circuit chips attached to the chip carrier, and a cap structure attached to the chip carrier, covering the one or more integrated circuit chips. A conductive grid structure is formed in the chip carrier and cap structure, the conductive structure having a plurality of meandering lines disposed in an x-direction, a y-direction, and a z-direction. The conductive grid structure is configured so as to detect an attempt to penetrate the IC module.

Abstract: A method and electrical structure for separating electronic components from one another joined by solder interconnections. An electronic module is joined to a substrate via a solder interconnection, whereby the electronic module has an electrical heating component residing within a bottom layer thereof adjacent a solder interconnection. Preferably, a chip carrier is joined to a board whereby the chip carrier has an electrical mesh plane for heating adjacent the solder interconnection. Resistive heat is generated within this electrical heating component either by applying an electrical current to the electrical heating component, or by non-contact inductively heating the layer in which such electrical heating component resides to generate resistive heat within the electrical heating component. The resistive heat is transferred to the solder interconnection to allow for localized melting of the solder interconnection and removal of the electronic components from one another.

Abstract: An integrated circuit structure and a method of manufacturing, wherein the method comprises forming a first via in an interconnect layer of the substrate, wherein the first via comprises a first size diameter; and forming a second via in the interconnect layer, wherein the second via comprises a second size diameter, the second size diameter being dimensioned larger than the first size diameter, wherein the second via comprises a non-uniform circumference, and wherein the substrate is configured in an approximately 1:1 ratio (i.e., approximately equal number) of the first and second vias. The first and second vias are laser formed or are formed by any of mechanical punching and photolithography. The second via is formed by sequentially forming multiple partially overlapping vias dimensioned and configured with the first size diameter. The first and second vias are arranged in a grid to allow for wiring of electronic devices.

Abstract: A dielectric substrate having an embedded inductor wherein each turn of the inductor traverses several layers such that the top and bottom of each turn of the inductor are parallel to each other but are in different layers and the sides of each turn of the inductor traverse at least one layer to connect the top and bottom of the inductor.