Abstract: A system and method are provided for exposing an imaging medium. The method uses a focal plane shutter system with two reversible motors controlled by a servo control processor. A belt connects the motors. One end of the belt is attached to a shaft of the first reversible motor. The other end of the belt is connected to a shaft of the second reversible motor. In the belt, there are a plurality of fixed width slits. The servo control processor selects one of the fixed width slits according to a desired exposure time setting. The two reversible motors move the belt during an imaging cycle. During the imaging cycle, the first motor winds the belt around its shaft. The second motor simultaneously unwinds the belt from around its shaft. The servo control processor controls the motors to accelerate the selected slit up to a constant imaging medium traversal speed. The constant traversal speed is also determined by the desired exposure time setting.

Abstract: On-the-fly video processing to implement two-dimensional algorithms is performed without a frame buffer or random-access memory, by using CCD delay elements whose clock rate is controlled by a phase synchronizing loop, to achieve precise vertical alignment of pixels where the chosen algorithm requires.

Abstract: A technique is provided for simultaneously displaying on a television screen juxtaposed pictures from two independent image sources. The required picture compression is achieved by storing analog samples of the video signals in an analog memory at one frequency and retrieving the samples at a higher frequency for display. A 2 to 1 picture compression is attained, for example, by retrieving the samples at twice the frequency at which they are stored.

Abstract: A logic system for charge-coupled device driver circuits includes a master oscillator for driving system logic circuits, which in turn generate signals for the non-bit-rate clock circuits. In addition, the system logic circuits generate a command which resets and synchronizes a separate resettable bit-rate oscillator to drive the bit-rate logic circuits which generate bit-rate clock waveforms. By maintaining separate oscillators for bit-rate and non-bit-rate functions, the logic system substantially reduces noise and therefore results in a clearer image from CCD area imaging array.