Patents by Inventor Hasibur Rahman

Hasibur Rahman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10819234
    Abstract: A system includes an inductor, and a first switch coupled between a first end of the inductor and a voltage supply node. The system also includes a second switch coupled between the first end of the inductor and a negative output supply node, wherein the second switch comprises a self-operated arrangement. The system also includes a third switch coupled between a second end of the inductor and a positive output supply node. The system also includes a fourth switch coupled between the second end of the inductor and a ground node. The system also includes a controller coupled to the first, second, third, and fourth switches.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: October 27, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ariel Dario Moctezuma, Hasibur Rahman, William Krenik, Yanqing Li
  • Patent number: 10770971
    Abstract: A system includes an inductor and a first switch coupled between a first end of the inductor and a voltage supply node. The system also includes a second switch coupled between the first end of the inductor and a negative output supply node. The system also includes a third switch coupled between a second end of the inductor and a positive output supply node. The system also includes a fourth switch coupled between the second end of the inductor and a ground node. The system also includes a controller coupled to the first, second, third, and fourth switches. The controller is configured to provide an inductor charge mode, a positive boost mode, a negative boost mode, a first rest state involving the first switch, and a second rest state involving the fourth switch.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: September 8, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Gary Franklin Chard, Ariel Dario Moctezuma, Hasibur Rahman, Alex Kwasi Nyavor Titriku, Srinath Hosur
  • Publication number: 20200099295
    Abstract: A system includes an inductor, and a first switch coupled between a first end of the inductor and a voltage supply node. The system also includes a second switch coupled between the first end of the inductor and a negative output supply node, wherein the second switch comprises a self-operated arrangement. The system also includes a third switch coupled between a second end of the inductor and a positive output supply node. The system also includes a fourth switch coupled between the second end of the inductor and a ground node. The system also includes a controller coupled to the first, second, third, and fourth switches.
    Type: Application
    Filed: May 31, 2019
    Publication date: March 26, 2020
    Inventors: Ariel Dario MOCTEZUMA, Hasibur RAHMAN, William KRENIK, Yanqing LI
  • Publication number: 20200099294
    Abstract: A system includes an inductor and a first switch coupled between a first end of the inductor and a voltage supply node. The system also includes a second switch coupled between the first end of the inductor and a negative output supply node. The system also includes a third switch coupled between a second end of the inductor and a positive output supply node. The system also includes a fourth switch coupled between the second end of the inductor and a ground node. The system also includes a controller coupled to the first, second, third, and fourth switches. The controller is configured to provide an inductor charge mode, a positive boost mode, a negative boost mode, a first rest state involving the first switch, and a second rest state involving the fourth switch.
    Type: Application
    Filed: May 31, 2019
    Publication date: March 26, 2020
    Inventors: Gary Franklin CHARD, Ariel Dario MOCTEZUMA, Hasibur RAHMAN, Alex Kwasi Nyavor TITRIKU, Srinath HOSUR
  • Patent number: 10079538
    Abstract: A circuit includes a charge pump to generate an output reference voltage. A first bootstrap refresh circuit receives the reference voltage from the charge pump and is coupled between first and second bootstrap nodes of a DC/DC converter. The first bootstrap refresh circuit supplies first charge current that is sourced from the first bootstrap node to the second bootstrap node based on a control signal indicating a first operating mode of the DC/DC converter. A second bootstrap refresh circuit receives the reference voltage from the charge pump and is coupled between the first and second bootstrap nodes of the DC/DC converter. The second bootstrap refresh circuit supplies second charge current from the second bootstrap node to the first bootstrap node based on the control signal indicating a second operating mode of the DC/DC converter.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: September 18, 2018
    Assignee: Texas Instruments Incorporated
    Inventors: Xiaochun Zhao, Hasibur Rahman, Artur Lewinski, Tulong Yang
  • Publication number: 20180109179
    Abstract: A circuit includes a charge pump to generate an output reference voltage. A first bootstrap refresh circuit receives the reference voltage from the charge pump and is coupled between first and second bootstrap nodes of a DC/DC converter. The first bootstrap refresh circuit supplies first charge current that is sourced from the first bootstrap node to the second bootstrap node based on a control signal indicating a first operating mode of the DC/DC converter. A second bootstrap refresh circuit receives the reference voltage from the charge pump and is coupled between the first and second bootstrap nodes of the DC/DC converter. The second bootstrap refresh circuit supplies second charge current from the second bootstrap node to the first bootstrap node based on the control signal indicating a second operating mode of the DC/DC converter.
    Type: Application
    Filed: October 18, 2016
    Publication date: April 19, 2018
    Inventors: XIAOCHUN ZHAO, HASIBUR RAHMAN, ARTUR LEWINSKI, Tulong Yang
  • Publication number: 20180018012
    Abstract: One example includes a power control system. The power control system includes an activation controller that is powered via a first power voltage generated via a first power supply and is configured to provide an enable signal. The activation controller can assert the enable signal in response to an input activation signal to control activation of a second power supply. The second power supply can generate a second power voltage in response to the enable signal being asserted. The second power voltage can be provided to regulate power associated with ancillary electronic circuitry. The system also includes a deactivation controller that is powered via the second power voltage and is configured to generate a disable signal to de-assert the enable signal in response to one of a plurality of predetermined deactivation conditions.
    Type: Application
    Filed: July 18, 2016
    Publication date: January 18, 2018
    Inventors: GEORGE KONNAIL, ANGELO PEREIRA, HASIBUR RAHMAN, XIAOCHUN ZHAO, ARTUR JULIUSZ LEWINSKI
  • Patent number: 9035458
    Abstract: An integrated circuit contains lower components in the substrate, a PMD layer, upper components over the PMD layer, lower contacts in the PMD layer connecting some upper components to some lower components, an ILD layer over the upper components, metal interconnect lines over the ILD layer, and upper contacts connecting some upper components to some metal interconnect lines, and also includes annular stacked contacts of lower annular contacts aligned with upper annular contacts. The lower contacts and upper contacts each have a metal liner and a contact metal on the liner. The lower annular contacts have at least one ring of liner metal and contact metal surrounding a pillar of PMD material, and the upper contacts have at least one ring of liner metal and contact metal surrounding a pillar of ILD material. The annular stacked contacts connect the metal interconnects to the lower components.
    Type: Grant
    Filed: January 20, 2014
    Date of Patent: May 19, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Scott Robert Summerfelt, Hasibur Rahman, John Paul Campbell
  • Publication number: 20140131781
    Abstract: An integrated circuit contains lower components in the substrate, a PMD layer, upper components over the PMD layer, lower contacts in the PMD layer connecting some upper components to some lower components, an ILD layer over the upper components, metal interconnect lines over the ILD layer, and upper contacts connecting some upper components to some metal interconnect lines, and also includes annular stacked contacts of lower annular contacts aligned with upper annular contacts. The lower contacts and upper contacts each have a metal liner and a contact metal on the liner. The lower annular contacts have at least one ring of liner metal and contact metal surrounding a pillar of PMD material, and the upper contacts have at least one ring of liner metal and contact metal surrounding a pillar of ILD material. The annular stacked contacts connect the metal interconnects to the lower components.
    Type: Application
    Filed: January 20, 2014
    Publication date: May 15, 2014
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Scott Robert Summerfelt, Hasibur Rahman, John Paul Campbell
  • Patent number: 8652855
    Abstract: An integrated circuit contains lower components in the substrate, a PMD layer, upper components over the PMD layer, lower contacts in the PMD layer connecting some upper components to some lower components, an ILD layer over the upper components, metal interconnect lines over the ILD layer, and upper contacts connecting some upper components to some metal interconnect lines, and also includes annular stacked contacts of lower annular contacts aligned with upper annular contacts. The lower contacts and upper contacts each have a metal liner and a contact metal on the liner. The lower annular contacts have at least one ring of liner metal and contact metal surrounding a pillar of PMD material, and the upper contacts have at least one ring of liner metal and contact metal surrounding a pillar of ILD material. The annular stacked contacts connect the metal interconnects to the lower components.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: February 18, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Scott Robert Summerfelt, Hasibur Rahman, John Paul Campbell
  • Publication number: 20130082314
    Abstract: An integrated circuit contains lower components in the substrate, a PMD layer, upper components over the PMD layer, lower contacts in the PMD layer connecting some upper components to some lower components, an ILD layer over the upper components, metal interconnect lines over the ILD layer, and upper contacts connecting some upper components to some metal interconnect lines, and also includes annular stacked contacts of lower annular contacts aligned with upper annular contacts. The lower contacts and upper contacts each have a metal liner and a contact metal on the liner. The lower annular contacts have at least one ring of liner metal and contact metal surrounding a pillar of PMD material, and the upper contacts have at least one ring of liner metal and contact metal surrounding a pillar of ILD material. The annular stacked contacts connect the metal interconnects to the lower components.
    Type: Application
    Filed: March 29, 2012
    Publication date: April 4, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Scott Robert Summerfelt, Hasibur Rahman, John Paul Campbell
  • Patent number: 7391241
    Abstract: A deglitch circuit utilizes a first flip-flop coupled to the input signal and a second flip-flop coupled to the output of a circuit with feedback from the output to gates to control first and second inputs to the first flip-flop. In an alternative arrangement, a counter is provided between the output of the first flip-flop and the input to the second flip-flop in order to provide flexibility and the possibility of a longer delay for the circuit.
    Type: Grant
    Filed: July 29, 2005
    Date of Patent: June 24, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Suribhotla V. Rajasekhar, Hasibur Rahman, Alexander Noam Teutsch, William E. Grose
  • Publication number: 20060103432
    Abstract: A deglitch circuit utilizes a first flip-flop coupled to the input signal and a second flip-flop coupled to the output of a circuit with feedback from the output to gates to control first and second inputs to the first flip-flop. In an alternative arrangement, a counter is provided between the output of the first flip-flop and the input to the second flip-flop in order to provide flexibility and the possibility of a longer delay for the circuit.
    Type: Application
    Filed: July 29, 2005
    Publication date: May 18, 2006
    Inventors: Suribhotla Rajasekhar, Hasibur Rahman, Alexander Teutsch, William Grose
  • Patent number: 7000138
    Abstract: An adaptive clock throttle 600 interfacing a clock generator 601 generating a high speed clock and a processing engine 602 operating in response to a processing clock. Adaptive clock throttle 600 generates a plurality of lower speed clocks from the high speed clock, estimates a duty cycle of the processing engine, and selectively gates one of the lower speed clocks to the processing engine as the processing clock to increase the duty cycle of the processing engine.
    Type: Grant
    Filed: June 7, 2001
    Date of Patent: February 14, 2006
    Assignee: Cirrus Logic, INC
    Inventors: Sanjay Ramakrishna Pillay, Raghunath Krishna Rao, Hasibur Rahman, Girish Subramaniam
  • Patent number: 6782300
    Abstract: A method of extracting a clock from a biphase encoded bit stream includes the step of detecting a stream of samples each having a sample size measured between consecutive bit phase transitions. A sample length is determined for each sample, the sample length approximating a number of least common multiples in the corresponding sample size. A preamble is detected from the sample lengths of a sequence of the samples and decoded to determine an expected logic level of the clock following a transition at an expected clock edge. The expected level of the clock is gated with the biphase encoded data to generate a control signal in advance of the opening of the time window. The control signal is then gated with the biphase encoded data to extract the clock edge after the time window has opened.
    Type: Grant
    Filed: December 5, 2000
    Date of Patent: August 24, 2004
    Assignee: Cirrus Logic, Inc.
    Inventors: Sanjay Ramakrishna Pillay, Hasibur Rahman
  • Publication number: 20030195645
    Abstract: A method of extracting a clock from a biphase encoded bit stream includes the step of detecting a stream of samples each having a sample size measured between consecutive bit phase transitions. A sample length is determined for each sample, the sample length approximating a number of least common multiples in the corresponding sample size. A preamble is detected from the sample lengths of a sequence of the samples and decoded to determine an expected logic level of the clock following a transition at an expected clock edge. The expected level of the clock is gated with the biphase encoded data to generate a control signal in advance of the opening of the time window. The control signal is then gated with the biphase encoded data to extract the clock edge after the time window has opened.
    Type: Application
    Filed: December 5, 2000
    Publication date: October 16, 2003
    Applicant: Cirrus Logic, Inc.
    Inventors: Sanjay Ramakrishna Pillay, Hasibur Rahman