Patents by Inventor Hasmik Lazaryan

Hasmik Lazaryan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for designing large standard-cell base integrated circuits
    Patent number: 6567967
    Abstract: An automated method of designing large digital integrated circuits using a software program to partition the design into physically realizable blocks and then create the connections between blocks so as to maximize operating speed and routability while minimizing the area of the resulting integrated circuit. Timing and physical constraints are generated for each physically realizable block so that standard-cell place and route software can create each block independently as if it were a separate integrated circuit.
    Type: Grant
    Filed: June 4, 2001
    Date of Patent: May 20, 2003
    Assignee: Monterey Design Systems, Inc.
    Inventors: Yaacov I. Greidinger, David S. Reed, Ara Markosian, Stephen P. Sample, Jonathan A. Frankle, Hasmik Lazaryan
  • Method for designing large standard-cell based integrated circuits
    Publication number: 20020087940
    Abstract: An automated method of designing large digital integrated circuits using a software program to partition the design into physically realizable blocks and then create the connections between blocks so as to maximize operating speed and routability while minimizing the area of the resulting integrated circuit. Timing and physical constraints are generated for each physically realizable block so that standard-cell place and route software can create each block independently as if it were a separate integrated circuit.
    Type: Application
    Filed: June 4, 2001
    Publication date: July 4, 2002
    Inventors: Yaacov I. Greidinger, David S. Reed, Ara Markosian, Stephen P. Sample, Jonathan A. Frankle, Hasmik Lazaryan
  • Method for designing large standard-cell based integrated circuits
    Publication number: 20020087939
    Abstract: An automated method of designing large digital integrated circuits using a software program to partition the design into physically realizable blocks then create the connections between blocks so as to maximize operating speed and routability while minimizing the area of the resulting integrated circuit. Timing and physical constraints are generated for each physically realizable block so that standard-cell place and route software can create each block independently as if it were a separate integrated circuit.
    Type: Application
    Filed: May 25, 2001
    Publication date: July 4, 2002
    Inventors: Yaacov I. Greidinger, David S. Reed, Ara Markosian, Stephen P. Sample, Jonathan A. Frankle, Hasmik Lazaryan