Abstract: A set of instructions executable at an integrated circuit is partitioned into multiple instruction blocks. A first and second instruction block are executed multiple times, including a first execution and a second execution. The first execution of the first instruction block is associated with a first set of executions, and the first execution of the second instruction block is associated with a second set of executions. A first amount of energy consumption representative of a member of the first set of executions is determined, and a second amount of energy consumption representative of a member of the second set of executions is determined. The first amount of energy is assigned to each member of the first set, and the second amount of energy is assigned to each member of the second set, and used to determine a total amount of energy consumption associated with execution of the set of instructions.

Abstract: A set of instructions executable at an integrated circuit is partitioned into multiple instruction blocks. A first and second instruction block are executed multiple times, including a first execution and a second execution. The first execution of the first instruction block is associated with a first set of executions, and the first execution of the second instruction block is associated with a second set of executions. A first amount of energy consumption representative of a member of the first set of executions is determined, and a second amount of energy consumption representative of a member of the second set of executions is determined. The first amount of energy is assigned to each member of the first set, and the second amount of energy is assigned to each member of the second set, and used to determine a total amount of energy consumption associated with execution of the set of instructions.

Abstract: A program stream is executed at a first processing engine, the program stream including multiple iterations of a first load instruction. An instruction loop is executed at a second processing engine separate from the first processing engine substantially in parallel with an execution of the program stream at the first processing engine for prefetching data from memory to a buffer for one or more iterations of the first load instruction of the program stream. The instruction loop represents a subset of a sequence of instructions between iterations of the first load instruction that affect an address value associated with the first load instruction. A confidence value associated with the instruction loop is modified based on a prefetch performance of one or more iterations of the first load instruction and it is determined whether to terminate execution of the instruction loop based on the confidence value.

Abstract: A first prefetch engine from a first plurality of prefetch engines is allocated to a first load instruction in response to a buffer miss of an iteration of the first load instruction in a program stream. The first plurality of prefetch engines include prefetch engines for prefetching data from memory to a buffer based on a predicted stride. A second prefetch engine from a second plurality of prefetch engines is allocated to the first load instruction in response to the buffer miss. The second plurality of prefetch engines include prefetch engines for prefetching data from memory to the buffer based on an instruction loop representative of a sequence of instructions that affect an address value associated with an allocated load instruction. One of the first or second prefetch engines is deallocated if the other prefetch engine achieves a prefetch performance greater than a first threshold value.

Abstract: Adjusting the confidence level of prefetch circuitry in generating outstanding prefetch address of a detected strided stream. In one example, the number of outstanding prefetches allowed is adjusted based on a determination of whether a prefetch to a prefetch address is used in a data processing system. With some systems, the higher the confidence level, the more outstanding prefetches are allowed.

Abstract: Generating a hashed value of the program counter in a data processing system. The hashed value can be used for prefetching in the data processing system. In some examples, the hashed value is used to identify whether a load instruction associated with the hashed value has an address that is part of a strided stream in an address stream. In some examples, the hashed value is a subset of bits of the bits of the program counter. In other examples, the hashed value may be derived in other ways from the program counter.

Abstract: Prefetching across a page boundary in a data processing system. The system determines whether a prefetch will cross a page boundary of memory, and if so, it determines whether a translation source has an entry corresponding to the virtual address of the prefetch. If the translation source has an entry corresponding the virtual address, a physical address of the virtual address is used to prefetch the information.