Patents by Inventor Hassan EDREES
Hassan EDREES has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11966544Abstract: An electronic device may have a display with touch sensors. One or more shielding layers may be interposed between the display and the touch sensors. The display may include transistors with gate conductors, a first planarization layer formed over the gate conductors, one or more contacts formed in a first source-drain layer within the first planarization layer, a second planarization layer formed on the first planarization layer, one or more data lines formed in a second source-drain layer within the second planarization layer, a third planarization layer formed on the second planarization layer, and a data line shielding structure formed at least partly in a third source-drain layer within the third planarization layer. The data line shielding structure may be a routing line, a blanket layer, a mesh layer formed in one or more metal layers, and/or a data line covering another data line.Type: GrantFiled: May 25, 2023Date of Patent: April 23, 2024Assignee: Apple Inc.Inventors: Shinya Ono, Suhwan Moon, Dong-Gwang Ha, Jiaxi Hu, Hao-Lin Chiu, Kwang Soon Park, Hassan Edrees, Wen-I Hsieh, Jiun-Jye Chang, Chin-Wei Lin, Kyung Wook Kim
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Publication number: 20240127758Abstract: A display may include an array of pixels that receive control signals from a chain of gate drivers. The pixels can be formed using semiconducting oxide transistors, whereas the gate drivers can be formed using silicon transistor. Each gate driver may include a shift register subcircuit and an output buffer subcircuit. The shift register subcircuit may include a first set of transistors at least partially controlled by one or more shift register clock signals. The output buffer subcircuit may include a second set of transistors at least partially controlled by one or more output buffer clock signals. The output buffer clock signals can toggle independently from the shift register clock signals. Operated in this way, the shift register clock signals can have pulse widths optimized for stability while the output buffer clock signals can have pulse widths optimized for speed.Type: ApplicationFiled: May 23, 2023Publication date: April 18, 2024Inventors: Shinya Ono, Chin-Wei Lin, Chen-Ming Chen, Hassan Edrees
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Patent number: 11922887Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to associated thin-film transistors. The diode may be coupled to drive transistor circuitry, a data loading transistor, and emission transistors. The drive transistor circuitry may include at least two transistor portions connected in series. The data loading transistor has a drain region connected to a data line and a source region connected directly to the drive transistor circuitry. The data line may be connected to and overlap the drain region of the data loading transistor. The data line and the source region of the data loading transistor are non-overlapping to reduce row-to-row crosstalk.Type: GrantFiled: July 6, 2021Date of Patent: March 5, 2024Assignee: Apple Inc.Inventors: Shinya Ono, Chin-Wei Lin, Chuan-Jung Lin, Gihoon Choo, Hassan Edrees, Hei Kam, Jung Yen Huang, Pei-En Chang, Rungrot Kitsomboonloha, Szu-Hsien Lee, Zino Lee
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Publication number: 20240036680Abstract: An electronic device may have a display with touch sensors. One or more shielding layers may be interposed between the display and the touch sensors. The display may include transistors with gate conductors, a first planarization layer formed over the gate conductors, one or more contacts formed in a first source-drain layer within the first planarization layer, a second planarization layer formed on the first planarization layer, one or more data lines formed in a second source-drain layer within the second planarization layer, a third planarization layer formed on the second planarization layer, and a data line shielding structure formed at least partly in a third source-drain layer within the third planarization layer. The data line shielding structure may be a routing line, a blanket layer, a mesh layer formed in one or more metal layers, and/or a data line covering another data line.Type: ApplicationFiled: May 25, 2023Publication date: February 1, 2024Inventors: Shinya Ono, Suhwan Moon, Dong-Gwang Ha, Jiaxi Hu, Hao-Lin Chiu, Kwang Soon Park, Hassan Edrees, Wen-I Hsieh, Jiun-Jye Chang, Chin-Wei Lin, Kyung Wook Kim
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Patent number: 11756481Abstract: Systems, methods, and devices are provided for mitigating visual artifacts by dynamically tuning bias voltages applied to display pixels. An electronic display may include a display pixel and a bias voltage supply. The bias voltage supply may supply a first bias voltage to the display pixel for a first subframe of a frame of image data. The bias voltage supply may supply a different second bias voltage to the display pixel for a second subframe of the frame of image data. This may mitigate certain image artifacts, such as flicker or variable refresh rate luminance difference, that could arise due to display pixel hysteresis that varies across subframes of the image frame.Type: GrantFiled: September 8, 2021Date of Patent: September 12, 2023Assignee: Apple Inc.Inventors: Hyunsoo Kim, Kingsuk Brahma, Myungjoon Choi, Yue Jack Chu, Li-Xuan Chuo, Hassan Edrees, Chin-Wei Lin, Hyunwoo Nho, Shinya Ono, Alex H. Pai, Jie Won Ryu, Yao Shi, Chaohao Wang
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Patent number: 11348533Abstract: A display may include an array of pixels, where each pixel in the array includes an organic light-emitting diode coupled to associated thin-film transistors. The thin-film transistors may be controlled using at least first and second horizontal scan line signals. Loading different data values into any given row in the array may cause the scan line signals to exhibit varying rise/fall times, which results in horizontal crosstalk and luminance non-uniformity across the display. The rise and fall times of the second scan line signal are crucial, so the second scan line signal is driven by two separate scan line drivers formed on both sides of the display. Only the fall time of the first scan line signal is crucial, so the first scan line signal is driven by only one peripheral scan line driver and is coupled to an auxiliary pull-down circuit that is only activated during the pull-down transition.Type: GrantFiled: May 1, 2020Date of Patent: May 31, 2022Assignee: Apple Inc.Inventors: Shinya Ono, Chin-Wei Lin, Gihoon Choo, Shiping Shen, Jie Won Ryu, Zino Lee, Hassan Edrees, Ting-Kuo Chang
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Publication number: 20220076627Abstract: Systems, methods, and devices are provided for mitigating visual artifacts by dynamically tuning bias voltages applied to display pixels. An electronic display may include a display pixel and a bias voltage supply. The bias voltage supply may supply a first bias voltage to the display pixel for a first subframe of a frame of image data. The bias voltage supply may supply a different second bias voltage to the display pixel for a second subframe of the frame of image data. This may mitigate certain image artifacts, such as flicker or variable refresh rate luminance difference, that could arise due to display pixel hysteresis that varies across subframes of the image frame.Type: ApplicationFiled: September 8, 2021Publication date: March 10, 2022Inventors: Hyunsoo Kim, Kingsuk Brahma, Myungjoon Choi, Yue Jack Chu, Li-Xuan Chuo, Hassan Edrees, Chin-Wei Lin, Hyunwoo Nho, Shinya Ono, Alex H. Pai, Jie Won Ryu, Yao Shi, Chaohao Wang
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Patent number: 11211020Abstract: A display may have rows and columns of pixels. Gate lines may be used to supply gate signals to rows of the pixels. Data lines may be used to supply data signals to columns of the pixels. The data lines may include alternating even and odd data lines. Data lines may be organized in pairs each of which includes one of the odd data lines and an adjacent one of the even data lines. Demultiplexer circuitry may be configured dynamically during data loading and pixel sensing operations. During data loading, data from display driver circuitry may be supplied, alternately to odd pairs of the data lines and even pairs of the data lines. During sensing, the demultiplexer circuitry may couple a pair of the even data lines to sensing circuitry in the display driver circuitry and then may couple a pair of the odd data lines to the sensing circuitry.Type: GrantFiled: March 29, 2019Date of Patent: December 28, 2021Assignee: Apple Inc.Inventors: Shinya Ono, Zino Lee, Gihoon Choo, Hassan Edrees, Chin-Wei Lin
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Patent number: 11127357Abstract: Techniques for implementing and/or operating an electronic device, which includes a display pixel that emits light to facilitate displaying an image during an emission period and a data driver coupled to the display pixel via a data line. The data driver generates a data line voltage signal based on image data that indicates target luminance of the display pixel in the image and supplies the data line voltage signal to the data line during a non-emission period preceding the emission period to facilitate writing the image to the display pixel. Additionally, the data driver supplies an intermediate voltage greater than a ground voltage to the data line during the emission period in which the image is displayed to facilitate reducing luminance variation in the image resulting from a leakage current flowing between an internal node of the display pixel and the data line during the emission period.Type: GrantFiled: April 16, 2020Date of Patent: September 21, 2021Assignee: APPLE INC.Inventors: Jie Won Ryu, Myungjoon Choi, Hyunsoo Kim, Hyunwoo Nho, Chin-Wei Lin, Shiping Shen, Kingsuk Brahma, Chaohao Wang, Shinya Ono, Alex H. Pai, Hassan Edrees
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Patent number: 11049457Abstract: A display may include an array of pixels, where each pixel in the array includes an organic light-emitting diode coupled to a drive transistor and other associated thin-film transistors. The array may be grouped into column pairs, where each column pair includes a first pixel column and a second pixel column that is mirrored with respect to the first pixel column. The drive transistors within each column pair may be formed towards the center of that column pair, whereas the data lines associated with that column pair may be formed along the outer peripheral edges of that column pair. Configured in this way, parasitic coupling between the data lines and any sensitive/floating nodes of the drive transistor may be substantially reduced, which mitigates pixel column crosstalk and ensures luminance uniformity across the display.Type: GrantFiled: April 17, 2020Date of Patent: June 29, 2021Assignee: Apple Inc.Inventors: Shinya Ono, Chin-Wei Lin, Chen-Ming Chen, Chun-Chieh Lin, Gihoon Choo, Hassan Edrees, Zino Lee
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Publication number: 20200335046Abstract: Techniques for implementing and/or operating an electronic device, which includes a display pixel that emits light to facilitate displaying an image during an emission period and a data driver coupled to the display pixel via a data line. The data driver generates a data line voltage signal based on image data that indicates target luminance of the display pixel in the image and supplies the data line voltage signal to the data line during a non-emission period preceding the emission period to facilitate writing the image to the display pixel. Additionally, the data driver supplies an intermediate voltage greater than a ground voltage to the data line during the emission period in which the image is displayed to facilitate reducing luminance variation in the image resulting from a leakage current flowing between an internal node of the display pixel and the data line during the emission period.Type: ApplicationFiled: April 16, 2020Publication date: October 22, 2020Inventors: Jie Won Ryu, Myungjoon Choi, Hyunsoo Kim, Hyunwoo Nho, Chin-Wei Lin, Shiping Shen, Kingsuk Brahma, Chaohao Wang, Shinya Ono, Alex H. Pai, Hassan Edrees
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Publication number: 20190228726Abstract: A display may have rows and columns of pixels. Gate lines may be used to supply gate signals to rows of the pixels. Data lines may be used to supply data signals to columns of the pixels. The data lines may include alternating even and odd data lines. Data lines may be organized in pairs each of which includes one of the odd data lines and an adjacent one of the even data lines. Demultiplexer circuitry may be configured dynamically during data loading and pixel sensing operations. During data loading, data from display driver circuitry may be supplied, alternately to odd pairs of the data lines and even pairs of the data lines. During sensing, the demultiplexer circuitry may couple a pair of the even data lines to sensing circuitry in the display driver circuitry and then may couple a pair of the odd data lines to the sensing circuitry.Type: ApplicationFiled: March 29, 2019Publication date: July 25, 2019Inventors: Shinya Ono, Zino Lee, Gihoon Choo, Hassan Edrees, Chin-Wei Lin
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Publication number: 20190140621Abstract: An electrical circuit assembly can include a semiconductor integrated circuit, such as fabricated including CMOS devices. A first lateral-mode resonator can be fabricated upon a surface of the semiconductor integrated circuit, such as including a deposited acoustic energy storage layer including a semiconductor material, a deposited piezoelectric layer acoustically coupled to the deposited acoustic energy storage layer, and a first conductive region electrically coupled to the deposited piezoelectric layer and electrically coupled to the semiconductor integrated circuit. The semiconductor integrated circuit can include one or more transistor structures, such as fabricated prior to fabrication of the lateral-mode resonator. Fabrication of the lateral-mode resonator can include low-temperature processing specified to avoid disrupting operational characteristics of the transistor structures.Type: ApplicationFiled: September 28, 2018Publication date: May 9, 2019Inventors: Hassan Edrees, Ioannis Kymissis, Peter Kinget
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Patent number: 10122345Abstract: An electrical circuit assembly can include a semiconductor integrated circuit, such as fabricated including CMOS devices. A first lateral-mode resonator can be fabricated upon a surface of the semiconductor integrated circuit, such as including a deposited acoustic energy storage layer including a semiconductor material, a deposited piezoelectric layer acoustically coupled to the deposited acoustic energy storage layer, and a first conductive region electrically coupled to the deposited piezoelectric layer and electrically coupled to the semiconductor integrated circuit. The semiconductor integrated circuit can include one or more transistor structures, such as fabricated prior to fabrication of the lateral-mode resonator. Fabrication of the lateral-mode resonator can include low-temperature processing specified to avoid disrupting operational characteristics of the transistor structures.Type: GrantFiled: June 26, 2014Date of Patent: November 6, 2018Assignee: The Trustees of Columbia University in the City of New YorkInventors: Hassan Edrees, Ioannis Kymissis, Peter Kinget
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Publication number: 20160191017Abstract: An electrical circuit assembly can include a semiconductor integrated circuit, such as fabricated including CMOS devices. A first lateral-mode resonator can be fabricated upon a surface of the semiconductor integrated circuit, such as including a deposited acoustic energy storage layer including a semiconductor material, a deposited piezoelectric layer acoustically coupled to the deposited acoustic energy storage layer, and a first conductive region electrically coupled to the deposited piezoelectric layer and electrically coupled to the semiconductor integrated circuit. The semiconductor integrated circuit can include one or more transistor structures, such as fabricated prior to fabrication of the lateral-mode resonator. Fabrication of the lateral-mode resonator can include low-temperature processing specified to avoid disrupting operational characteristics of the transistor structures.Type: ApplicationFiled: June 26, 2014Publication date: June 30, 2016Inventors: Hassan EDREES, Ioannis KYMISSISS, Peter KINGET