Patents by Inventor Hassan Kianinejad

Hassan Kianinejad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and system for designing FPGA based on hardware requirements defined in source code
    Patent number: 10169513
    Abstract: According to one embodiment, a source code is parsed to identify a first routine to perform a first function and a second routine to perform a second function. A control signaling topology is determined between the first routine and the second routine based on one or more statements associated with the first routine and the second routine defined in the source code. A first logic block is allocated describing a first hardware configuration representing the first function of the first routine. A second logic block is allocated describing a second hardware configuration representing the second function of the second routine. A register-transfer level (RTL) netlist is generated based on the first logic block and the second logic block. The second logic block is to perform the second function dependent upon the first function performed by the first logic block based on the control signaling topology.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: January 1, 2019
    Assignee: BAIDU USA LLC
    Inventors: Davy Huang, Jia Feng, Hassan Kianinejad, Yanyan Zhang, Manjiang Zhang
  • METHOD AND SYSTEM FOR DESIGNING FPGA BASED ON HARDWARE REQUIREMENTS DEFINED IN SOURCE CODE
    Publication number: 20170323045
    Abstract: According to one embodiment, a source code is parsed to identify a first routine to perform a first function and a second routine to perform a second function. A control signaling topology is determined between the first routine and the second routine based on one or more statements associated with the first routine and the second routine defined in the source code. A first logic block is allocated describing a first hardware configuration representing the first function of the first routine. A second logic block is allocated describing a second hardware configuration representing the second function of the second routine. A register-transfer level (RTL) netlist is generated based on the first logic block and the second logic block. The second logic block is to perform the second function dependent upon the first function performed by the first logic block based on the control signaling topology.
    Type: Application
    Filed: May 6, 2016
    Publication date: November 9, 2017
    Inventors: Davy Huang, Jia Feng, Hassan Kianinejad, Yanyan Zhang, Manjiang Zhang