Abstract: A wired communication system includes a bidirectional channel for sending information in one direction at a high bandwidth and sending control information for configuring a transmitter in the other direction at a lower bandwidth. Embodiments of the disclosure may use a primary transmitter output stage in the transmitter and a primary receiver input stage in the receiver to send and receive data or a clock, for example. An auxiliary transmitter output stage in the receiver and auxiliary receiver input stage in the transmitter send and receive control information for configuring the transmitter to efficiently send data over a wired channel.

Abstract: A wired communication system includes a bidirectional channel for sending information in one direction at a high bandwidth and sending control information for configuring a transmitter in the other direction at a lower bandwidth. Embodiments of the disclosure may use a primary transmitter output stage in the transmitter and a primary receiver input stage in the receiver to send and receive data or a clock, for example. An auxiliary transmitter output stage in the receiver and auxiliary receiver input stage in the transmitter send and receive control information for configuring the transmitter to efficiently send data over a wired channel.

Abstract: A high-speed clock generator device includes a phase-interpolator (PI) circuit, a smoothing block, and inverter-based low-pass filters. The PI circuit receives a multiple clock signals with different phase angles and generates an output clock signal having a correct phase angle. The smoothing block smooths the clock signals with different phase angles and generates a number of smooth clock signals featuring improved linearity. The inverter-based low-pass filters filter harmonics of the clock signals with different phase angles.

Abstract: A high-speed clock generator device includes a phase-interpolator (PI) circuit, a smoothing block, and inverter-based low-pass filters. The PI circuit receives a multiple clock signals with different phase angles and generates an output clock signal having a correct phase angle. The smoothing block smooths the clock signals with different phase angles and generates a number of smooth clock signals featuring improved linearity. The inverter-based low-pass filters filter harmonics of the clock signals with different phase angles.

Abstract: A device for passive equalization and slew-rate control of a signal includes a first branch and a second branch. The first branch includes a first driver coupled in series with an equalization capacitor. The second branch includes a second driver coupled in series with a resistor. The second branch may be coupled in parallel to the first branch. The first branch may be configurable to enable either passive equalization or slew-rate control of the signal based on a mode control signal.

Abstract: A device for high-speed clock generation may include an injection locking-ring oscillator (ILRO) configured to receive one or more input clock signals and to generate multiple clock signals with different equally spaced phase angles. A phase-interpolator (PI) circuit may be configured to receive the multiple coarse spaced clock signals and to generate an output clock signal having a correct phase angle. The PI circuit may include a smoothing block that may be configured to smooth the multiple clock signals with different phase angles and to generate multiple smooth clock signals. A pulling block may be configured to pull edges of the multiple smooth clock signals closer to one another.

Abstract: A device for passive equalization and slew-rate control of a signal includes a first branch that includes a first driver coupled in series with an equalization capacitor, and a second branch that includes a second driver coupled in series with a resistor. The second branch may be coupled in parallel to the first branch, and the first branch may be configurable to enable one of passive equalization or slew-rate control of the signal based on a mode control signal.

Abstract: Methods and apparatuses are described for a DSP receiver with an analog-to-digital converter (ADC) having high speed, low BER performance with low power and area requirements. Speed is increased for multi-path ADC configurations by resolving a conventional bottleneck. ADC performance is improved by integrating calibration and error detection and correction, such as distributed offset calibration and redundant comparators. Power and area requirements are dramatically reduced by using low BER rectification to nearly halve the number of comparators in a conventional high speed, low BER flash ADC.

Abstract: A device for high-speed clock generation may include an injection locking-ring oscillator (ILRO) configured to receive one or more input clock signals and to generate multiple clock signals with different equally spaced phase angles. A phase-interpolator (PI) circuit may be configured to receive the multiple coarse spaced clock signals and to generate an output clock signal having a correct phase angle. The PI circuit may include a smoothing block that may be configured to smooth the multiple clock signals with different phase angles and to generate multiple smooth clock signals. A pulling block may be configured to pull edges of the multiple smooth clock signals closer to one another.

Abstract: A communication system is described that includes a transmitter to transmit data using one or more drivers. The drivers may drive the data in a manner that accords with pre-emphasis being selectively enabled or disabled for each driver. The pre-emphasis, when enabled, is applied by corresponding driver. The drivers may also be programmably selected and enabled or disabled. The transmitter also includes one or more driver selection circuits. The driver selection circuits may be configured to select one or more of the drivers to transmit the data, to selectively enable or disable pre-emphasis to be applied by each of the selected drivers, and to provide the data, or representations thereof, to the selected drivers.

Abstract: Methods and apparatuses are described for a DSP receiver with an analog-to-digital converter (ADC) having high speed, low BER performance with low power and area requirements. Speed is increased for multi-path ADC configurations by resolving a conventional bottleneck. ADC performance is improved by integrating calibration and error detection and correction, such as distributed offset calibration and redundant comparators. Power and area requirements are dramatically reduced by using low BER rectification to nearly halve the number of comparators in a conventional high speed, low BER flash ADC.

Abstract: A voltage controlled oscillator (VCO) may include a stack of a plurality of non-connected inductors that are magnetically and/or electrically through capacitor (AC) coupled to each other and not directly physically connected to each other. The plurality of inductors includes a first inductor connected to a supply voltage and a second inductor connected to a VCO control voltage. The VCO may include a first varactor having a gate coupled to a first terminal of the second inductor to receive the VCO control voltage, a second varactor having a gate coupled to a second terminal of the second inductor to receive the VCO control voltage, and an oscillator sub-circuit coupled to first and second terminals of the first inductor. In one example implementation, the second inductor may contribute to the overall inductance of the inductor stack and provide AC decoupling and/or DC coupling between the VCO control voltage and the varactor(s).

Abstract: In one embodiment the present invention includes a method of calibrating the frequency response of a transmitter comprising generating a plurality of calibration tones across a frequency range, coupling the plurality of calibration tones to an input of said transmitter, detecting the plurality of calibration tones at an output in said transmitter, and in accordance therewith, generating a plurality of calibration values, receiving digital data to be transmitted, the digital data comprising a plurality of frequency components in said frequency range, and calibrating said frequency components of said digital data using the calibration values.