Patents by Inventor Hassan Maher

Hassan Maher has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090179234
    Abstract: A field effect transistor having a T-gate (10), the gate comprising a neck portion (16) and a T-bar portion (18) overhanging the neck portion, wherein the neck portion (16) comprises a plurality of spaced pillars (20). By forming the neck portion from a plurality of spaced pillars the area of contact between the gate and the channel, or “effective gate width”, is reduced whilst the T-bar portion (18) ensures electrical continuity through the gate by bridging the pillars (20). This reduces the input gate capacitance, thereby giving an FET having an increased device performance.
    Type: Application
    Filed: September 22, 2005
    Publication date: July 16, 2009
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS, N.V.
    Inventors: Hassan Maher, Pierre M.M. Baudet
  • Publication number: 20090026501
    Abstract: A ED-HEMT structure includes a buffer layer (4) including a doped layer (18), a channel layer (6), a barrier layer (8), and a second doped layer (20). An enhancement mode HEMT gate (12) is formed in a via extending through the second doped layer (20) and a depletion mode HEMT structure is formed over the second doped layer (20). The layer sequence allows the formation of both enhancement and depletion mode HEMTs in the same structure with good properties.
    Type: Application
    Filed: December 13, 2005
    Publication date: January 29, 2009
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS, N.V.
    Inventors: Hassan Maher, Pierre Baudet
  • Publication number: 20080093630
    Abstract: A HEMT has a substrate (2), buffer layer (4), channel layer (8), spacer layer (10), delta doped layer (12), Schottky barrier layer (14) and cap layer (18) and metal layer (20), the latter forming a Schottky barrier with the underlying semiconductor. The channel may be of GaInAs and the barrier (4), spacer (10) and Schottky barrier layers (14) may be of AlInAs. An additional thin layer for example of GaAs is added between the Schottky barrier layer (14) and metallic layer (18) to enhance the Schottky barrier height without creating excessive defects.
    Type: Application
    Filed: July 6, 2005
    Publication date: April 24, 2008
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS, N.V.
    Inventors: Hassan Maher, Pierre M.M. Baudet
  • Publication number: 20070278519
    Abstract: The invention relates to a transistor structure with both enhancement and depletion mode transistors. In order to allow good control over the manufacture of both transistors, a first Schottky layer (10) and a second Schottky layer (12) are used made of first and second semiconductor materials respectively. The first and second materials having band gaps of at least 0.5V. For an n-type transistor the second Schottky layer has a low conduction band discontinuity with the first Schottky layer. Both the first and the second Schottky layers are used as etch stops in the method for making the transistor. The transistor is preferably a HEMT.
    Type: Application
    Filed: September 22, 2005
    Publication date: December 6, 2007
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS, N.V.
    Inventors: Pierre Baudet, Hassan Maher