Abstract: Current-generation circuitry, comprising: a plurality of candidate current sources operable to generate respective candidate currents; an output current source operable to generate an output current; comparator circuitry; and control circuitry operable to control the current sources and the comparator circuitry to: in an adjustment step, generate an adjustment current by selecting one of the candidate currents or by summing together a plurality of the candidate currents, and calibrate at least a plurality of the candidate current sources; and in a calibration step, following the adjustment step, generate a reference current by selecting one of the candidate currents generated by the candidate current sources calibrated in the adjustment step or by summing together a plurality of the candidate currents generated by those candidate current sources, and calibrate the output current source by comparing its output current to that reference current and adjusting a control signal applied to that output current sourc

Abstract: The present invention relates to resistance calibration and in particular to resistance calibration in the context of semiconductor integrated circuitry.

Abstract: Current-generation circuitry, comprising: a plurality of candidate current sources operable to generate respective candidate currents; an output current source operable to generate an output current; comparator circuitry; and control circuitry operable to control the current sources and the comparator circuitry to: in an adjustment step, generate an adjustment current by selecting one of the candidate currents or by summing together a plurality of the candidate currents, and calibrate at least a plurality of the candidate current sources; and in a calibration step, following the adjustment step, generate a reference current by selecting one of the candidate currents generated by the candidate current sources calibrated in the adjustment step or by summing together a plurality of the candidate currents generated by those candidate current sources, and calibrate the output current source by comparing its output current to that reference current and adjusting a control signal applied to that output current sourc

Abstract: The present invention relates to resistance calibration and in particular to resistance calibration in the context of semiconductor integrated circuitry.

Abstract: Systematic transmit IQ phase and amplitude imbalances in the transmit chain of a wireless local area network (WLAN) cause a corresponding systematic shift in the roots of a constellation diagram. Additional random phase noise in the transmit chain will cause a further Gaussian distribution of points in the constellation diagram about the systematically shifted roots. This random distribution represents a true error vector magnitude (EVM). By transmitting a known training sequence through the transmit chain, which it is known will be shifted to all of the systematically shifted roots in the constellation diagram, the Gaussian spread around those shifted roots can be analysed to determine the true EVM.

Abstract: Systematic transmit IQ phase and amplitude imbalances in the transmit chain of a wireless local area network (WLAN) cause a corresponding systematic shift in the roots of a constellation diagram. Additional random phase noise in the transmit chain will cause a further Gaussian distribution of points in the constellation diagram about the systematically shifted roots. This random distribution represents a true error vector magnitude (EVM). By transmitting a known training sequence through the transmit chain, which it is known will be shifted to all of the systematically shifted roots in the constellation diagram, the Gaussian spread around those shifted roots can be analysed to determine the true EVM.

Abstract: An automatic gain control (AGC) circuit has an automatic gain controlled amplifier connected in series with a DC blocking capacitor. A reference DC voltage is selectively applied to an input of the automatic gain controlled amplifier and to an output of the DC blocking capacitor output so as to cause the DC blocking capacitor to store a charge proportional to a DC voltage offset introduced by the controllable gain amplifier. The selectively application of the reference DC voltage is momentarily applied for a duration of less than about 1 microsecond and preferably about 0.4 microseconds. The AGC circuit, including both the amplifier and capacitor, are fabricated as an integrated circuit device.

Abstract: An automatic gain control (AGC) circuit has an automatic gain controlled amplifier connected in series with a DC blocking capacitor. A reference DC voltage is selectively applied to an input of the automatic gain controlled amplifier and to an output of the DC blocking capacitor output so as to cause the DC blocking capacitor to store a charge proportional to a DC voltage offset introduced by the controllable gain amplifier. The selectively application of the reference DC voltage is momentarily applied for a duration of less than about 1 microsecond and preferably about 0.4 microseconds. The AGC circuit, including both the amplifier and capacitor, are fabricated as an integrated circuit device.