Patents by Inventor Hassane S. Azar
Hassane S. Azar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11792451Abstract: Embodiments of the present invention provide a low-latency approach for local or remote application streaming that reaches high FPS targets without overloading the available streaming bandwidth, for example, by limiting the bit rate to the same value that is used by traditional 60 FPS streaming solutions. A client device and server device cooperate to actively monitor and control a video stream to maintain an acceptable balance between latency and video quality by adjusting the frequency or resolution when necessary to improve the streaming experience. When the server device captures and transmits frames at a higher rate, the software stack executing on the client device is able to display frames with less delay, even on a display device limited to 60 Hz, thereby achieving additional latency reduction.Type: GrantFiled: March 9, 2021Date of Patent: October 17, 2023Assignee: NVIDIA CorporationInventors: Alexander McAuley, Haitao Xue, Hassane S. Azar, Bipin Todur, Alan Larson, Reza Marandian Hagh
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Publication number: 20210195262Abstract: Embodiments of the present invention provide a low-latency approach for local or remote application streaming that reaches high FPS targets without overloading the available streaming bandwidth, for example, by limiting the bit rate to the same value that is used by traditional 60 FPS streaming solutions. A client device and server device cooperate to actively monitor and control a video stream to maintain an acceptable balance between latency and video quality by adjusting the frequency or resolution when necessary to improve the streaming experience. When the server device captures and transmits frames at a higher rate, the software stack executing on the client device is able to display frames with less delay, even on a display device limited to 60 Hz, thereby achieving additional latency reduction.Type: ApplicationFiled: March 9, 2021Publication date: June 24, 2021Inventors: Alexander McAuley, Haitao Xue, Hassane S. Azar, Bipin Todur, Alan Larson, Reza Marandian Hagh
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Patent number: 10979744Abstract: Embodiments of the present invention provide a low-latency approach for local or remote application streaming that reaches high FPS targets without overloading the available streaming bandwidth, for example, by limiting the bit rate to the same value that is used by traditional 60 FPS streaming solutions. A client device and server device cooperate to actively monitor and control a video stream to maintain an acceptable balance between latency and video quality by adjusting the frequency or resolution when necessary to improve the streaming experience. When the server device captures and transmits frames at a higher rate, the software stack executing on the client device is able to display frames with less delay, even on a display device limited to 60 Hz, thereby achieving additional latency reduction.Type: GrantFiled: November 2, 2018Date of Patent: April 13, 2021Assignee: NVIDIA CorporationInventors: Alexander McAuley, Haitao Xue, Hassane S. Azar, Bipin Todur, Alan Larson, Reza Marandian Hagh
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Patent number: 10242462Abstract: A video encoder, a method of encoding a frame of video data, and a three-dimensional modeling system producing an encoded video stream are disclosed herein. In one embodiment, the method includes: (1) receiving from an application a frame of video data to be encoded, (2) determining a gamer's attention area for the frame of video data and (3) changing an encoding of the frame of video data by allocating bits for the frame based upon the gamer's attention area.Type: GrantFiled: April 2, 2013Date of Patent: March 26, 2019Assignee: Nvidia CorporationInventor: Hassane S. Azar
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Patent number: 10237563Abstract: A system and method are provided for a 3D modeling system with which an encoded video stream is produced. The system includes a content engine, an encoder, and a fixed function engine. The fixed function engine receives content information from the content engine. The fixed function engine produces encoder information from the content information. The encoder uses the encoder information to produce an encoded video stream having at least one of a higher quality and a lower bandwidth than a video stream encoded without the encoder information.Type: GrantFiled: December 11, 2012Date of Patent: March 19, 2019Assignee: Nvidia CorporationInventors: Hassane S. Azar, Bryan Dudash, Rochelle Pereira, Dawid Pajak
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Patent number: 9984504Abstract: A system and method are provided for improving video encoding using content information. A three-dimensional (3D) modeling system produces an encoded video stream. The system includes a content engine, a renderer, and a video encoder. The renderer receives 3D model information from the content engine relating and to produces corresponding two-dimensional (2D) images. The video encoder receives the 2D images and produce a corresponding encoded video stream. The video encoder receives content information from the content engine, transforms the content information into encoder control information, and controls the video encoder using the encoder control information.Type: GrantFiled: October 1, 2012Date of Patent: May 29, 2018Assignee: Nvidia CorporationInventors: Hassane S. Azar, Stefan Eckart, Dawid Pajak, Bryan Dudash, Swagat Mohapatra
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Patent number: 9483845Abstract: A video frame compression system includes a rendering engine that provides a current video frame and current additional rendering information. Additionally, the video frame compression system includes a warping engine that generates a warped video frame, wherein the warped video frame is a transformation of a previous video frame that is based on the current additional rendering information. Further, the video frame compression system includes a video encoder that compresses the current video frame by using the warped video frame as a reference frame and separately compresses the current additional rendering information. Still further, the video frame compression system includes a packetizer that provides main and auxiliary data streams corresponding to the compressed current video frame and the compressed current additional rendering information, respectively. A video frame decompression system and methods of video frame compression and decompression are also provided.Type: GrantFiled: April 26, 2013Date of Patent: November 1, 2016Assignee: Nvidia CorporationInventors: Hassane S Azar, Dawid Pajak, Stefan Eckart, Swagat Mohapatra
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Publication number: 20140358990Abstract: A communications system includes a mobile device that is coupled to a network and has a mobile application requiring fulfillment and a personal computer that is coupled to the network and has computer data entry and display capabilities. Additionally, the communications system includes a mobile applications processor that is coupled to the personal computer and provides a mobile device interaction, wherein the mobile device interaction includes fulfillment of the mobile application with the computer data entry and display capabilities. A method of operating a communications system and a method of fulfilling mobile applications are also provided.Type: ApplicationFiled: June 3, 2013Publication date: December 4, 2014Inventors: Jen-Hsun Huang, Hassane S. Azar, Arman Toorians, Philip J. Carmack
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Publication number: 20140321757Abstract: A video frame compression system includes a rendering engine that provides a current video frame and current additional rendering information. Additionally, the video frame compression system includes a warping engine that generates a warped video frame, wherein the warped video frame is a transformation of a previous video frame that is based on the current additional rendering information. Further, the video frame compression system includes a video encoder that compresses the current video frame by using the warped video frame as a reference frame and separately compresses the current additional rendering information. Still further, the video frame compression system includes a packetizer that provides main and auxiliary data streams corresponding to the compressed current video frame and the compressed current additional rendering information, respectively. A video frame decompression system and methods of video frame compression and decompression are also provided.Type: ApplicationFiled: April 26, 2013Publication date: October 30, 2014Applicant: Nvidia CorporationInventors: Hassane S Azar, Dawid Pajak, Stefan Eckart, Swagat Mohapatra
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Publication number: 20140292751Abstract: A video encoder, a method of encoding a frame of video data, and a three-dimensional modeling system producing an encoded video stream are disclosed herein. In one embodiment, the method includes: (1) receiving from an application a frame of video data to be encoded, (2) determining a gamer's attention area for the frame of video data and (3) changing an encoding of the frame of video data by allocating bits for the frame based upon the gamer's attention area.Type: ApplicationFiled: April 2, 2013Publication date: October 2, 2014Applicant: Nvidia CorporationInventor: Hassane S. Azar
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Publication number: 20140161173Abstract: A system and method are provided for a 3D modeling system with which an encoded video stream is produced. The system includes a content engine, an encoder, and a fixed function engine. The fixed function engine receives content information from the content engine. The fixed function engine produces encoder information from the content information. The encoder uses the encoder information to produce an encoded video stream having at least one of a higher quality and a lower bandwidth than a video stream encoded without the encoder information.Type: ApplicationFiled: December 11, 2012Publication date: June 12, 2014Applicant: Nvidia CorporationInventors: Hassane S. Azar, Bryan Dudash, Rochelle Pereira, Dawid Pajak
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Publication number: 20140122558Abstract: Embodiments of the invention provide techniques for offloading certain classes of compute operations from battery-powered handheld devices operating in a wireless private area network (WPAN) to devices with relatively greater computing capabilities operating in the WPAN that are not power-limited by batteries. In order to offload certain classes of compute operations, a handheld device may discover an offload device within a local network via a discovery mechanism, and offload large or complex compute operations to the offload device by utilizing one or more low-latency communications protocols, such as Wi-Fi Direct or a combination of Wi-Fi Direct and real-time transport protocol (RTP). One advantage of the disclosed techniques is that the techniques allow handheld devices to perform complex operations without substantially impacting battery life.Type: ApplicationFiled: October 29, 2012Publication date: May 1, 2014Applicant: NVIDIA CORPORATIONInventor: Hassane S. AZAR
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Publication number: 20140092209Abstract: A system and method are provided for improving video encoding using content information. A three-dimensional (3D) modeling system produces an encoded video stream. The system includes a content engine, a renderer, and a video encoder. The renderer receives 3D model information from the content engine relating and to produces corresponding two-dimensional (2D) images. The video encoder receives the 2D images and produce a corresponding encoded video stream. The video encoder receives content information from the content engine, transforms the content information into encoder control information, and controls the video encoder using the encoder control information.Type: ApplicationFiled: October 1, 2012Publication date: April 3, 2014Applicant: NVIDIA CORPORATIONInventors: Hassane S. Azar, Stefan Eckart, Dawid Pajak, Bryan Dudash, Swagat Mohapatra
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Patent number: 8520009Abstract: Video filtering using a programmable graphics processor is described. The programmable graphics processor may be programmed to complete a plurality of video filtering operations in a single pass through a fragment-processing pipeline within the programmable graphics processor. Video filtering functions such as deinterlacing, chroma up-sampling, scaling, and deblocking may be performed by the fragment-processing pipeline. The fragment-processing pipeline may be programmed to perform motion adaptive deinterlacing, wherein a spatially variant filter determines, on a pixel basis, whether a “bob”, a “blend”, or a “weave” operation should be used to process an interlaced image.Type: GrantFiled: December 29, 2009Date of Patent: August 27, 2013Assignee: NVIDIA CorporationInventors: Stephen D. Lew, Garry W. Amann, Hassane S. Azar
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Patent number: 8149234Abstract: A system is presented that is configured to reduce power consumption when performing processing tasks. The system includes a first processing entity capable of performing a set of operations, and a second processing entity configured to consume less power than the first processing entity and capable of performing a subset of operations that is part of the set of operations. During system operation, the second processing entity is configured to perform the subset of operations instead of the first processing entity.Type: GrantFiled: October 25, 2011Date of Patent: April 3, 2012Assignee: NVIDIA CorporationInventors: Hassane S. Azar, Franck R. Diard, Amit Parikh, Xun Wang
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Publication number: 20120042190Abstract: A system is presented that is configured to reduce power consumption when performing processing tasks. The system includes a first processing entity capable of performing a set of operations, and a second processing entity configured to consume less power than the first processing entity and capable of performing a subset of operations that is part of the set of operations. During system operation, the second processing entity is configured to perform the subset of operations instead of the first processing entity.Type: ApplicationFiled: October 25, 2011Publication date: February 16, 2012Inventors: Hassane S. AZAR, Franck R. Diard, Amit Parikh, Xun Wang
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Patent number: 8054316Abstract: A system and method for adjusting pictures minimizes the impact on graphics processing performance of a discrete processor. A hybrid system configuration includes the discrete processor and an integrated processor, where the discrete processor typically consumes more power and provides greater processing performance compared with the integrated processor. A picture is produced by a video or graphics engine of a discrete processor within a hybrid system. Each picture is then transferred to a back buffer in the host processing memory. The picture is analyzed to produce picture analysis results that are used to generate adjustment settings. The back buffer is swapped to become the front buffer and the adjustment settings are applied to the picture by an integrated processor to display an adjusted picture. The adjustment may be used in conjunction with power saving techniques to maintain the image quality when display backlighting is reduced.Type: GrantFiled: November 14, 2008Date of Patent: November 8, 2011Assignee: NVIDIA CorporationInventors: Hassane S. Azar, Franck R. Diard, Amit Parikh, Xun Wang
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Patent number: 7974485Abstract: Split-frame post-processing techniques are used in a programmable video post processing engine. A frame of video data is divided into a processing region and a control region that contain either different portions of the frame or copies of a portion of the frame. Post-processing operations are performed for the processing region but not for the control region. The processing and control regions are then displayed simultaneously on the same display device (e.g., side by side), facilitating visual comparisons of images with and without post-processing.Type: GrantFiled: October 27, 2005Date of Patent: July 5, 2011Assignee: NVIDIA CorporationInventors: Hassane S. Azar, Franck R. Diard
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Patent number: 7965898Abstract: A system and method for decoding high definition video content using multiple processors reduces the likelihood of dropping video frames. Each of the multiple processors produces and stores a portion of a decoded video frame in its dedicated frame buffer. A region of a reference frame that is needed to produce a first portion of a decoded video frame, but that is not stored in the frame buffer coupled to the processor that will decode the first portion, is copied to the frame buffer. The size of the region needed may vary based on a maximum possible motion vector offset. The size of the region that is copied may be dynamic and based on a maximum motion vector offset for each particular reference frame.Type: GrantFiled: October 28, 2005Date of Patent: June 21, 2011Assignee: NVIDIA CorporationInventors: Franck R. Diard, Hassane S. Azar
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Patent number: 7876378Abstract: Video filtering using a programmable graphics processor is described. The programmable graphics processor may be programmed to complete a plurality of video filtering operations in a single pass through a fragment-processing pipeline within the programmable graphics processor. Video filtering functions such as deinterlacing, chroma up-sampling, scaling, and deblocking may be performed by the fragment-processing pipeline. The fragment-processing pipeline may be programmed to perform motion adaptive deinterlacing, wherein a spatially variant filter determines, on a pixel basis, whether a “bob”, a “blend”, or a “weave” operation should be used to process an interlaced image.Type: GrantFiled: December 14, 2007Date of Patent: January 25, 2011Assignee: NVIDIA CorporationInventors: Stephen D. Lew, Garry W. Amann, Hassane S. Azar