Abstract: A numerically controlled oscillator includes a phase accumulator which generates sequences of phase word phase signals. A demultiplexer 104 directs the odd and even numbered phase angle words of the sequence to identical but independent lookup tables to generate corresponding waveform signals. The wave form signals at the output of each lookup table occur at one-half the frequency of the system clock. A multiplexer 108 interleaves the output signals from the lookup tables to provide a properly ordered sequence of waveform signals at the frequency of the system clock. The maximum system clock frequency can be approximately twice the maximum operating frequency of each lookup table.

Abstract: An electronically programmable gate array comprises a plurality of rows of logic cells with each cell having a plurality of inputs, at least one output, and a plurality of electronically programmable voltage levels for configuring the cell. A plurality of sets of interconnect lines are formed in the array with one set of interconnect lines provided between adjacent rows of logic cells with electronically programmable contacts connecting inputs and an output of each cell in a row of cells with two adjacent sets of interconnect lines. Each row of logic cells preferably includes alternating three-input cells and two-input cells. Each electronically programmable voltage level comprises two voltage alterable resistors serially connected between first and second voltage potentials. Each electronically programmable interconnect comprises a voltage alterable resistor.