Abstract: In a semiconductor device in which power is supplied from an external power supply system, a first power supply system is connected to first terminals of power supply and ground and a digital inner circuit. The inner circuit includes a clock signal generating circuit, a driver for the clock signal, and circuits operating in response to the clock signal. A second power supply system is connected to second terminals of power supply and ground, the input terminal, the output terminal, and a digital interface circuit. The second power supply system is independent of the first power supply system. The interface circuit includes a MOS transistor for pulling up or down the input terminal and an output circuit which includes a MOS transistor driving an output terminal. The first power supply system is separated from the second power supply system, and the inner circuit is connected to the interface circuit through only signal lines.

Abstract: A test mode setting arrangement provided in a microcomputer includes an internal memory, a plurality of pins and a central processing unit, the central processing unit being allowed to access the internal memory or an external memory depending on a logic level of a mode signal applied to the microcomputer, the arrangement basically features: a first unit for resetting the central processing unit in response to a reset control signal applied thereto, the reset control signal and the mode signal exhibiting essentially the same maximum voltage; a second unit for changing the output thereof in response to the logic level change of the mode signal, the second unit issuing an output which is applied to the central processing unit as a test mode initiating signal; and a third unit coupled to receive the mode signal and the output of the second unit, the third unit producing two signals which selects the access of the central processing unit to one of the internal and external memories.