Abstract: The invention provides a power supply including at least one power output port, at least one status alert component, and at least one output port status monitoring module. The status alert component generates at least one visual prompt based on an alert signal. The output port status monitoring module includes at least one temperature sensor adjacent to the power output port, a microcontroller connected to the temperature sensor and sensing an output current from the power output port, and a reset signal generator connected to the microcontroller. The microcontroller comprises at least one port status alert condition that takes a temperature and the output current of the power output port as decision factors. The microcontroller outputs the alert signal to the status alert component when the port status alert condition is met and maintains the status until a reset signal provided by the reset signal generator is received.

Abstract: A wearable device is illustrated. The wearable device has a body, at least one light emitting unit, at least one light sensing unit and an action recognition module. The wearable device is suitable for wearing on a movable part of a user. The light emitting unit is disposed on an inner side of the body, wherein the light emitting unit emits a light beam illuminating at least a portion of the movable part. The light sensing unit operatively senses the light beam reflected by the at least portion of the movable part and generates a light sensing signal. The action recognition module is configured to operatively determine a function that corresponds to an action of the user.

Abstract: The present invention relates to methods for the diagnosis and treatment of melanoma. In particular, the invention relates to methods for the diagnosis and treatment of early stage melanoma by measuring the expression of one or more autoantibodies selected from the group consisting of anti-ZBTB7B, anti-PRKCH, anti-TP53, anti-PCTK1, anti-PQBP1, anti-UBE2V1, anti-IRF4, anti-MAPK8_tv2, anti-MSN and anti-TPM1. Further, the present invention relates to kits comprising one or more reagents and/or devices when used in performing the methods for the diagnosis and treatment of melanoma.

Abstract: The present invention relates to methods for the diagnosis and treatment of melanoma. In particular, the invention relates to methods for the diagnosis and treatment of early stage melanoma by measuring the expression of one or more autoantibodies selected from the group consisting of anti-ZBTB7B, anti-PRKCH, anti-TP53, anti-PCTK1, anti-PQBP1, anti-UBE2V1, anti-IRF4, anti-MAPK8_tv2, anti-MSN and anti-TPM1. Further, the present invention relates to kits comprising one or more reagents and/or devices when used in performing the methods for the diagnosis and treatment of melanoma.

Abstract: A memory assist apparatus includes a detection circuit and a compensation circuit. The detection circuit is configured to provide a detection signal indicating whether a bit line configured to provide read access to a data bit stored at a memory bit cell has a voltage below a predetermined threshold. The compensation circuit is configured to pull down the voltage of the bit line if the detection signal indicates that the voltage of the bit line is below the predetermined threshold.

Abstract: Apparatus and methods for providing a high density memory array with reduced read access time are disclosed. Multiple split bit lines are arranged along columns of adjacent memory bit cells. A multiple input sense amplifier is coupled to the multiple split bit lines. The loading on the multiple split bit line is reduced, and the corresponding read speed of the memory array is enhanced over the prior art. The sense amplifier and the memory bit cells have a common cell pitch layout height so that no silicon area penalty arises due to the use of the multiple split bit lines and sense amplifiers. Increased memory array efficiency is achieved.

Abstract: A memory assist apparatus includes a detection circuit and a compensation circuit. The detection circuit is configured to provide a detection signal indicating whether a bit line configured to provide read access to a data bit stored at a memory bit cell has a voltage below a predetermined threshold. The compensation circuit is configured to pull down the voltage of the bit line if the detection signal indicates that the voltage of the bit line is below the predetermined threshold.

Abstract: A memory assist apparatus includes a detection circuit and a compensation circuit. The detection circuit is configured to provide a detection signal indicating whether a bit line configured to provide read access to a data bit stored at a memory bit cell has a voltage below a predetermined threshold. The compensation circuit is configured to pull down the voltage of the bit line if the detection signal indicates that the voltage of the bit line is below the predetermined threshold.

Abstract: In at least one embodiment, a multiplexer has a plurality of sub-circuits, and each of the plurality of sub-circuits has a first transistor, a second transistor, and a third transistor. Drains of the first transistors are coupled with a first terminal of a fourth transistor, and drains of the second transistors are coupled with a second terminal of the fourth transistor. In at least one embodiment, a method of outputting data using the multiplexer includes turning on the second transistor of a selected one of the plurality of sub-circuits responsive to a clock signal and address information. The second transistor of a non-selected one of the plurality of sub-circuits is turned off. The fourth transistor is turned on responsive to the clock signal.

Abstract: A memory assist apparatus includes a detection circuit and a compensation circuit. The detection circuit is configured to provide a detection signal indicating whether a bit line configured to provide read access to a data bit stored at a memory bit cell has a voltage below a predetermined threshold. The compensation circuit is configured to pull down the voltage of the bit line if the detection signal indicates that the voltage of the bit line is below the predetermined threshold.

Abstract: A multiplexing circuit includes a plurality of first circuits and a second circuit coupled to outputs of the plurality of first circuits. A first circuit of the plurality of first circuits is configured to receive a first data line as a first input and a clock signal as a second input, and provide an output signal to a first circuit output. After the first circuit is selected for use, the clock signal, a first sub-circuit of the first circuit coupled to the second circuit, and the second circuit are configured to provide a first output logic level to the output signal based on a first data logic level of the first data line; and a second sub-circuit of the first circuit coupled to the first circuit output is configured to provide a second output logic level to the output signal based on a second data logic level of the first data line.

Abstract: A multiplexing circuit includes a plurality of first circuits and a second circuit coupled to outputs of the plurality of first circuits. A first circuit of the plurality of first circuits is configured to receive a first data line as a first input and a clock signal as a second input, and provide an output signal to a first circuit output. After the first circuit is selected for use, the clock signal, a first sub-circuit of the first circuit coupled to the second circuit, and the second circuit are configured to provide a first output logic level to the output signal based on a first data logic level of the first data line; and a second sub-circuit of the first circuit coupled to the first circuit output is configured to provide a second output logic level to the output signal based on a second data logic level of the first data line.

Abstract: Apparatus and methods for providing a high density memory array with reduced read access time are disclosed. Multiple split bit lines are arranged along columns of adjacent memory bit cells. A multiple input sense amplifier is coupled to the multiple split bit lines. The loading on the multiple split bit line is reduced, and the corresponding read speed of the memory array is enhanced over the prior art. The sense amplifier and the memory bit cells have a common cell pitch layout height so that no silicon area penalty arises due to the use of the multiple split bit lines and sense amplifiers. Increased memory array efficiency is achieved.

Abstract: A database system is disclosed. The database system includes a common data repository, a document indexing database and a query engine. The common data repository is configured to store data in a common data table and is associated with a data object. The document indexing database is configured to store a data structure model that is associated with a unique document type. The data structure model is configured to facilitate retrieval of data stored in the common data table. The query engine is communicatively linked to the document indexing database and the common data repository. The query engine is configured to use the data structure model to retrieve data from the common data table.