Patents by Inventor Hau Tao
Hau Tao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230387038Abstract: A semiconductor device includes an interposer disposed on a substrate. A first major surface of the interposer faces the substrate. A system on a chip is disposed on a second major surface of the interposer. The second major surface of the interposer opposes the first major surface of the interposer. A plurality of first passive devices is disposed in the first major surface of the interposer. A plurality of second passive devices is disposed on the second major surface of the interposer. The second passive devices are different devices than the first passive devices.Type: ApplicationFiled: August 7, 2023Publication date: November 30, 2023Inventors: Cheng-Chieh HSIEH, Hau TAO, Yung-Tien KUO
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Patent number: 11830822Abstract: A semiconductor device includes an interposer disposed on a substrate. A first major surface of the interposer faces the substrate. A system on a chip is disposed on a second major surface of the interposer. The second major surface of the interposer opposes the first major surface of the interposer. A plurality of first passive devices is disposed in the first major surface of the interposer. A plurality of second passive devices is disposed on the second major surface of the interposer. The second passive devices are different devices than the first passive devices.Type: GrantFiled: February 16, 2023Date of Patent: November 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Chieh Hsieh, Hau Tao, Yung-Tien Kuo
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Publication number: 20230197631Abstract: A semiconductor device includes an interposer disposed on a substrate. A first major surface of the interposer faces the substrate. A system on a chip is disposed on a second major surface of the interposer. The second major surface of the interposer opposes the first major surface of the interposer. A plurality of first passive devices is disposed in the first major surface of the interposer. A plurality of second passive devices is disposed on the second major surface of the interposer. The second passive devices are different devices than the first passive devices.Type: ApplicationFiled: February 16, 2023Publication date: June 22, 2023Inventors: Cheng-Chieh HSIEH, Hau TAO, Yung-Tien KUO
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Patent number: 11587883Abstract: A semiconductor device includes an interposer disposed on a substrate. A first major surface of the interposer faces the substrate. A system on a chip is disposed on a second major surface of the interposer. The second major surface of the interposer opposes the first major surface of the interposer. A plurality of first passive devices is disposed in the first major surface of the interposer. A plurality of second passive devices is disposed on the second major surface of the interposer. The second passive devices are different devices than the first passive devices.Type: GrantFiled: February 1, 2021Date of Patent: February 21, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Chieh Hsieh, Hau Tao, Yung-Tien Kuo
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Publication number: 20210159187Abstract: A semiconductor device includes an interposer disposed on a substrate. A first major surface of the interposer faces the substrate. A system on a chip is disposed on a second major surface of the interposer. The second major surface of the interposer opposes the first major surface of the interposer. A plurality of first passive devices is disposed in the first major surface of the interposer. A plurality of second passive devices is disposed on the second major surface of the interposer. The second passive devices are different devices than the first passive devices.Type: ApplicationFiled: February 1, 2021Publication date: May 27, 2021Inventors: Cheng-Chieh HSIEH, Hau TAO, Yung-Tien KUO
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Patent number: 10910321Abstract: A semiconductor device includes an interposer disposed on a substrate. A first major surface of the interposer faces the substrate. A system on a chip is disposed on a second major surface of the interposer. The second major surface of the interposer opposes the first major surface of the interposer. A plurality of first passive devices is disposed in the first major surface of the interposer. A plurality of second passive devices is disposed on the second major surface of the interposer. The second passive devices are different devices than the first passive devices.Type: GrantFiled: November 26, 2018Date of Patent: February 2, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Chieh Hsieh, Hau Tao, Yung-Tien Kuo
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Patent number: 10861830Abstract: A link device with a large density routing is attached to a package in order to provide a high-density interconnect pathway to interconnect semiconductor devices. In an embodiment the package is an integrated fan out package. The link device may be bonded on either side of the package, and the package may optionally comprise through package vias. The link device may also be an integrated passive device that includes resistors, inductor, and capacitor components.Type: GrantFiled: January 10, 2020Date of Patent: December 8, 2020Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chao-Yang Yeh, Ming-Tsun Lin, Hau Tao
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Publication number: 20200152606Abstract: A link device with a large density routing is attached to a package in order to provide a high-density interconnect pathway to interconnect semiconductor devices. In an embodiment the package is an integrated fan out package. The link device may be bonded on either side of the package, and the package may optionally comprise through package vias. The link device may also be an integrated passive device that includes resistors, inductor, and capacitor components.Type: ApplicationFiled: January 10, 2020Publication date: May 14, 2020Inventors: Chao-Yang Yeh, Ming-Tsun Lin, Hau Tao
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Patent number: 10535638Abstract: A link device with a large density routing is attached to a package in order to provide a high-density interconnect pathway to interconnect semiconductor devices. In an embodiment the package is an integrated fan out package. The link device may be bonded on either side of the package, and the package may optionally comprise through package vias. The link device may also be an integrated passive device that includes resistors, inductor, and capacitor components.Type: GrantFiled: April 8, 2019Date of Patent: January 14, 2020Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chao-Yang Yeh, Ming-Tsun Lin, Hau Tao
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Publication number: 20190237435Abstract: A link device with a large density routing is attached to a package in order to provide a high-density interconnect pathway to interconnect semiconductor devices. In an embodiment the package is an integrated fan out package. The link device may be bonded on either side of the package, and the package may optionally comprise through package vias. The link device may also be an integrated passive device that includes resistors, inductor, and capacitor components.Type: ApplicationFiled: April 8, 2019Publication date: August 1, 2019Inventors: Chao-Yang Yeh, Ming-Tsun Lin, Hau Tao
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Publication number: 20190164905Abstract: A semiconductor device includes an interposer disposed on a substrate. A first major surface of the interposer faces the substrate. A system on a chip is disposed on a second major surface of the interposer. The second major surface of the interposer opposes the first major surface of the interposer. A plurality of first passive devices is disposed in the first major surface of the interposer. A plurality of second passive devices is disposed on the second major surface of the interposer. The second passive devices are different devices than the first passive devices.Type: ApplicationFiled: November 26, 2018Publication date: May 30, 2019Inventors: Cheng-Chieh HSIEH, Hau TAO, Yung-Tien KUO
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Patent number: 10262974Abstract: A link device with a large density routing is attached to a package in order to provide a high-density interconnect pathway to interconnect semiconductor devices. In an embodiment the package is an integrated fan out package. The link device may be bonded on either side of the package, and the package may optionally comprise through package vias. The link device may also be an integrated passive device that includes resistors, inductor, and capacitor components.Type: GrantFiled: February 1, 2018Date of Patent: April 16, 2019Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chao-Yang Yeh, Ming-Tsun Lin, Hau Tao
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Patent number: 10002854Abstract: A link device with a large density routing is attached to a package in order to provide a high-density interconnect pathway to interconnect semiconductor devices. In an embodiment the package is an integrated fan out package. The link device may be bonded on either side of the package, and the package may optionally comprise through package vias. The link device may also be an integrated passive device that includes resistors, inductor, and capacitor components.Type: GrantFiled: April 12, 2017Date of Patent: June 19, 2018Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chao-Yang Yeh, Ming-Tsun Lin, Hau Tao
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Publication number: 20180158802Abstract: A link device with a large density routing is attached to a package in order to provide a high-density interconnect pathway to interconnect semiconductor devices. In an embodiment the package is an integrated fan out package. The link device may be bonded on either side of the package, and the package may optionally comprise through package vias. The link device may also be an integrated passive device that includes resistors, inductor, and capacitor components.Type: ApplicationFiled: February 1, 2018Publication date: June 7, 2018Inventors: Chao-Yang Yeh, Ming-Tsun Lin, Hau Tao
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Patent number: 9741688Abstract: A link device with a large density routing is attached to a package in order to provide a high-density interconnect pathway to interconnect semiconductor devices. In an embodiment the package is an integrated fan out package. The link device may be bonded on either side of the package, and the package may optionally comprise through package vias. The link device may also be an integrated passive device that includes resistors, inductor, and capacitor components.Type: GrantFiled: July 1, 2016Date of Patent: August 22, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chao-Yang Yeh, Ming-Tsun Lin, Hau Tao
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Publication number: 20170221863Abstract: A link device with a large density routing is attached to a package in order to provide a high-density interconnect pathway to interconnect semiconductor devices. In an embodiment the package is an integrated fan out package. The link device may be bonded on either side of the package, and the package may optionally comprise through package vias. The link device may also be an integrated passive device that includes resistors, inductor, and capacitor components.Type: ApplicationFiled: April 12, 2017Publication date: August 3, 2017Inventors: Chao-Yang Yeh, Ming-Tsun Lin, Hau Tao
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Publication number: 20160315066Abstract: A link device with a large density routing is attached to a package in order to provide a high-density interconnect pathway to interconnect semiconductor devices. In an embodiment the package is an integrated fan out package. The link device may be bonded on either side of the package, and the package may optionally comprise through package vias. The link device may also be an integrated passive device that includes resistors, inductor, and capacitor components.Type: ApplicationFiled: July 1, 2016Publication date: October 27, 2016Inventors: Chao-Yang Yeh, Ming-Tsun Lin, Hau Tao
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Patent number: 9385110Abstract: A link device with a large density routing is attached to a package in order to provide a high-density interconnect pathway to interconnect semiconductor devices. In an embodiment the package is an integrated fan out package. The link device may be bonded on either side of the package, and the package may optionally comprise through package vias. The link device may also be an integrated passive device that includes resistors, inductor, and capacitor components.Type: GrantFiled: August 19, 2014Date of Patent: July 5, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chao-Yang Yeh, Ming-Tsun Lin, Hau Tao
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Publication number: 20150371951Abstract: A link device with a large density routing is attached to a package in order to provide a high-density interconnect pathway to interconnect semiconductor devices. In an embodiment the package is an integrated fan out package. The link device may be bonded on either side of the package, and the package may optionally comprise through package vias. The link device may also be an integrated passive device that includes resistors, inductor, and capacitor components.Type: ApplicationFiled: August 19, 2014Publication date: December 24, 2015Inventors: Chao-Yang Yeh, Ming-Tsun Lin, Hau Tao