Patents by Inventor Hau-Yu Lin
Hau-Yu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11908749Abstract: A method includes: providing a first gate electrode over the substrate; forming a first pair of spacers on two sides of the first gate electrode; removing the first gate electrode to form a first trench between the first pair of spacers; depositing a dielectric layer in the first trench; depositing a first layer over the dielectric layer; removing the first layer from the first trench; and depositing a work function layer over the dielectric layer in the first trench.Type: GrantFiled: November 21, 2022Date of Patent: February 20, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yi-Jing Lee, Ya-Yun Cheng, Hau-Yu Lin, I-Sheng Chen, Chia-Ming Hsu, Chih-Hsin Ko, Clement Hsingjen Wann
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Patent number: 11854898Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.Type: GrantFiled: May 17, 2021Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sung-Li Wang, Neng-Kuo Chen, Ding-Kang Shih, Meng-Chun Chang, Yi-An Lin, Gin-Chen Huang, Chen-Feng Hsu, Hau-Yu Lin, Chih-Hsin Ko, Sey-Ping Sun, Clement Hsingjen Wann
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Publication number: 20230079483Abstract: A method includes: providing a first gate electrode over the substrate; forming a first pair of spacers on two sides of the first gate electrode; removing the first gate electrode to form a first trench between the first pair of spacers; depositing a dielectric layer in the first trench; depositing a first layer over the dielectric layer; removing the first layer from the first trench; and depositing a work function layer over the dielectric layer in the first trench.Type: ApplicationFiled: November 21, 2022Publication date: March 16, 2023Inventors: YI-JING LEE, YA-YUN CHENG, HAU-YU LIN, I-SHENG CHEN, CHIA-MING HSU, CHIH-HSIN KO, CLEMENT HSINGJEN WANN
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Patent number: 11508627Abstract: A method includes: providing a substrate; forming a first pair of source/drain regions in the substrate; disposing an interlayer dielectric layer over the substrate, the interlayer dielectric layer having a first trench between the first pair of source/drain regions; depositing a dielectric layer in the first trench; depositing a barrier layer over the dielectric layer; performing an operation on the substrate; removing the barrier layer from the first trench to expose the dielectric layer subsequent to the operation; and depositing a work function layer over the dielectric layer in the first trench.Type: GrantFiled: October 9, 2020Date of Patent: November 22, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yi-Jing Lee, Ya-Yun Cheng, Hau-Yu Lin, I-Sheng Chen, Chia-Ming Hsu, Chih-Hsin Ko, Clement Hsingjen Wann
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Patent number: 11362000Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.Type: GrantFiled: May 1, 2020Date of Patent: June 14, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sung-Li Wang, Neng-Kuo Chen, Ding-Kang Shih, Meng-Chun Chang, Yi-An Lin, Gin-Chen Huang, Chen-Feng Hsu, Hau-Yu Lin, Chih-Hsin Ko, Sey-Ping Sun, Clement Hsingjen Wann
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Publication number: 20210272849Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.Type: ApplicationFiled: May 17, 2021Publication date: September 2, 2021Inventors: Sung-Li Wang, Neng-Kuo Chen, Ding-Kang Shih, Meng-Chun Chang, Yi-An Lin, Gin-Chen Huang, Chen-Feng Hsu, Hau-Yu Lin, Chih-Hsin Ko, Sey-Ping Sun, Clement Hsingjen Wann
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Patent number: 10978451Abstract: An embodiment complimentary metal-oxide-semiconductor (CMOS) device and an embodiment method of forming the same are provided. The embodiment CMOS device includes an n-type metal-oxide-semiconductor (NMOS) having a titanium-containing layer interposed between a first metal contact and an NMOS source and a second metal contact and an NMOS drain and a p-type metal-oxide-semiconductor (PMOS) having a PMOS source and a PMOS drain, the PMOS source having a first titanium-containing region facing a third metal contact, the PMOS drain including a second titanium-containing region facing a fourth metal contact.Type: GrantFiled: December 11, 2019Date of Patent: April 13, 2021Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Clement Hsingjen Wann, Chih-Hsin Ko, Cheng-Hsien Wu, Ding-Kang Shih, Hau-Yu Lin
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Publication number: 20210028069Abstract: A method includes: providing a substrate; forming a first pair of source/drain regions in the substrate; disposing an interlayer dielectric layer over the substrate, the interlayer dielectric layer having a first trench between the first pair of source/drain regions; depositing a dielectric layer in the first trench; depositing a barrier layer over the dielectric layer; performing an operation on the substrate; removing the barrier layer from the first trench to expose the dielectric layer subsequent to the operation; and depositing a work function layer over the dielectric layer in the first trench.Type: ApplicationFiled: October 9, 2020Publication date: January 28, 2021Inventors: YI-JING LEE, YA-YUN CHENG, HAU-YU LIN, I-SHENG CHEN, CHIA-MING HSU, CHIH-HSIN KO, CLEMENT HSINGJEN WANN
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Patent number: 10804163Abstract: A method of forming a semiconductor structure includes: providing a substrate; forming a first pair of source/drain regions in the substrate; disposing an interlayer dielectric layer over the substrate, the interlayer dielectric layer having a first trench between the first pair of source/drain regions; depositing a dielectric layer in the first trench; depositing a barrier layer over the dielectric layer; removing the barrier layer from the first trench to expose the dielectric layer; depositing a work function layer over the dielectric layer in the first trench; and depositing a conductive layer over the work function layer in the first trench.Type: GrantFiled: April 1, 2019Date of Patent: October 13, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yi-Jing Lee, Ya-Yun Cheng, Hau-Yu Lin, I-Sheng Chen, Chia-Ming Hsu, Chih-Hsin Ko, Clement Hsingjen Wann
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Publication number: 20200258784Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.Type: ApplicationFiled: May 1, 2020Publication date: August 13, 2020Inventors: Sung-Li Wang, Neng-Kuo Chen, Ding-Kang Shih, Meng-Chun Chang, Yi-An Lin, Gin-Chen Huang, Chen-Feng Hsu, Hau-Yu Lin, Chih-Hsin Ko, Sey-Ping Sun, Clement Hsingjen Wann
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Patent number: 10651091Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.Type: GrantFiled: April 22, 2019Date of Patent: May 12, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sung-Li Wang, Neng-Kuo Chen, Ding-Kang Shih, Meng-Chun Chang, Yi-An Lin, Gin-Chen Huang, Chen-Feng Hsu, Hau-Yu Lin, Chih-Hsin Ko, Sey-Ping Sun, Clement Hsingjen Wann
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Publication number: 20200135589Abstract: A method of forming a semiconductor structure includes: providing a substrate; forming a first pair of source/drain regions in the substrate; disposing an interlayer dielectric layer over the substrate, the interlayer dielectric layer having a first trench between the first pair of source/drain regions; depositing a dielectric layer in the first trench; depositing a barrier layer over the dielectric layer; removing the barrier layer from the first trench to expose the dielectric layer; depositing a work function layer over the dielectric layer in the first trench; and depositing a conductive layer over the work function layer in the first trench.Type: ApplicationFiled: April 1, 2019Publication date: April 30, 2020Inventors: YI-JING LEE, YA-YUN CHENG, HAU-YU LIN, I-SHENG CHEN, CHIA-MING HSU, CHIH-HSIN KO, CLEMENT HSINGJEN WANN
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Publication number: 20200119013Abstract: An embodiment complimentary metal-oxide-semiconductor (CMOS) device and an embodiment method of forming the same are provided. The embodiment CMOS device includes an n-type metal-oxide-semiconductor (NMOS) having a titanium-containing layer interposed between a first metal contact and an NMOS source and a second metal contact and an NMOS drain and a p-type metal-oxide-semiconductor (PMOS) having a PMOS source and a PMOS drain, the PMOS source having a first titanium-containing region facing a third metal contact, the PMOS drain including a second titanium-containing region facing a fourth metal contact.Type: ApplicationFiled: December 11, 2019Publication date: April 16, 2020Inventors: Clement Hsingjen Wann, Chih-Hsin Ko, Cheng-Hsien Wu, Ding-Kang Shih, Hau-Yu Lin
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Patent number: 10510754Abstract: An embodiment complimentary metal-oxide-semiconductor (CMOS) device and an embodiment method of forming the same are provided. The embodiment CMOS device includes an n-type metal-oxide-semiconductor (NMOS) having a titanium-containing layer interposed between a first metal contact and an NMOS source and a second metal contact and an NMOS drain and a p-type metal-oxide-semiconductor (PMOS) having a PMOS source and a PMOS drain, the PMOS source having a first titanium-containing region facing a third metal contact, the PMOS drain including a second titanium-containing region facing a fourth metal contact.Type: GrantFiled: November 29, 2018Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Clement Hsingjen Wann, Chih-Hsin Ko, Cheng-Hsien Wu, Ding-Kang Shih, Hau-Yu Lin
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Publication number: 20190252261Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.Type: ApplicationFiled: April 22, 2019Publication date: August 15, 2019Inventors: Sung-Li Wang, Neng-Kuo Chen, Ding-Kang Shih, Meng-Chun Chang, Yi-An Lin, Gin-Chen Huang, Chen-Feng Hsu, Hau-Yu Lin, Chih-Hsin Ko, Sey-Ping Sun, Clement Hsingjen Wann
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Patent number: 10304826Abstract: An embodiment complimentary metal-oxide-semiconductor (CMOS) device and an embodiment method of forming the same are provided. The embodiment CMOS device includes an n-type metal-oxide-semiconductor (NMOS) having a titanium-containing layer interposed between a first metal contact and an NMOS source and a second metal contact and an NMOS drain and a p-type metal-oxide-semiconductor (PMOS) having a PMOS source and a PMOS drain, the PMOS source having a first titanium-containing region facing a third metal contact, the PMOS drain including a second titanium-containing region facing a fourth metal contact.Type: GrantFiled: December 28, 2012Date of Patent: May 28, 2019Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Clement Hsingjen Wann, Chih-Hsin Ko, Cheng-Hsien Wu, Ding-Kang Shih, Hau-Yu Lin
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Patent number: 10269649Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.Type: GrantFiled: March 28, 2018Date of Patent: April 23, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sung-Li Wang, Neng-Kuo Chen, Ding-Kang Shih, Meng-Chun Chang, Yi-An Lin, Gin-Chen Huang, Chen-Feng Hsu, Hau-Yu Lin, Chih-Hsin Ko, Sey-Ping Sun, Clement Hsingjen Wann
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Publication number: 20190096885Abstract: An embodiment complimentary metal-oxide-semiconductor (CMOS) device and an embodiment method of forming the same are provided. The embodiment CMOS device includes an n-type metal-oxide-semiconductor (NMOS) having a titanium-containing layer interposed between a first metal contact and an NMOS source and a second metal contact and an NMOS drain and a p-type metal-oxide-semiconductor (PMOS) having a PMOS source and a PMOS drain, the PMOS source having a first titanium-containing region facing a third metal contact, the PMOS drain including a second titanium-containing region facing a fourth metal contact.Type: ApplicationFiled: November 29, 2018Publication date: March 28, 2019Inventors: Clement Hsingjen Wann, Chih-Hsin Ko, Cheng-Hsien Wu, Ding-Kang Shih, Hau-Yu Lin
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Publication number: 20180219077Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.Type: ApplicationFiled: March 28, 2018Publication date: August 2, 2018Inventors: Sung-Li Wang, Neng-Kuo Chen, Ding-Kang Shih, Meng-Chun Chang, Yi-An Lin, Gin-Chen Huang, Chen-Feng Hsu, Hau-Yu Lin, Chih-Hsin Ko, Sey-Ping Sun, Clement Hsingjen Wann
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Patent number: 9941367Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.Type: GrantFiled: August 2, 2016Date of Patent: April 10, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sung-Li Wang, Neng-Kuo Chen, Ding-Kang Shih, Meng-Chun Chang, Yi-An Lin, Gin-Chen Huang, Chen-Feng Hsu, Hau-Yu Lin, Chih-Hsin Ko, Sey-Ping Sun, Clement Hsingjen Wann