Patents by Inventor Hau-Yung Chen

Hau-Yung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240072411
    Abstract: An electronic device includes a metal back cover, a metal frame, a first antenna module and a second antenna module. The metal frame includes a first and a second disconnection portion, a first and a second connection portion. The first and the second connection portion are connected to the metal back cover. The first disconnection portion is separated from the first connection portion, the metal back cover and the second disconnection portion to form a first slot. The second disconnection portion is connected to the second connection portion and is separated from the metal back cover to form a second slot. The first antenna module is connected to the first disconnection portion, and forms a first antenna path. The second antenna module is connected to the second disconnection portion, and forms a second and a third antenna path with the second disconnection portion and the metal back cover.
    Type: Application
    Filed: July 28, 2023
    Publication date: February 29, 2024
    Applicant: Pegatron Corporation
    Inventors: Chien-Yi Wu, Hau Yuen Tan, Chao-Hsu Wu, Chih-Wei Liao, Chia-Hung Chen, Chen-Kuang Wang, Wen-Hgin Chuang, Chia-Hong Chen, Hsi Yung Chen
  • Patent number: 10078721
    Abstract: Systems and techniques are described for determining a resistance of a conducting structure. The conducting structure can be partitioned into a set of polygons based on (1) equipotential lines and (2) boundaries of the conducting structure. Next, a matrix equation can be constructed, wherein for at least one polygon in the set of polygons, electric potentials of boundary elements on the boundaries of the polygon are represented by linear combinations of electric potentials of two or more equipotential lines. The resistance of the conducting structure can then be determined by solving the matrix equation.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: September 18, 2018
    Assignee: Synopsys, Inc.
    Inventors: Xiaoxu Cheng, Jingyu Xu, Hau-Yung Chen, Dick Liu
  • Publication number: 20170351803
    Abstract: Systems and techniques are described for determining a resistance of a conducting structure. The conducting structure can be partitioned into a set of polygons based on (1) equipotential lines and (2) boundaries of the conducting structure. Next, a matrix equation can be constructed, wherein for at least one polygon in the set of polygons, electric potentials of boundary elements on the boundaries of the polygon are represented by linear combinations of electric potentials of two or more equipotential lines. The resistance of the conducting structure can then be determined by solving the matrix equation.
    Type: Application
    Filed: June 3, 2016
    Publication date: December 7, 2017
    Applicant: Synopsys, Inc.
    Inventors: Xiaoxu Cheng, Jingyu Xu, Hau-Yung Chen, Dick Liu
  • Publication number: 20060280245
    Abstract: A method and apparatus is provided for generating various binary addresses for use in decoding MPEG video data. One or more n-bit counters and mutiplexers are used to generate such binary addresses. Different binary addresses can be generated by the same n-bit counter by swapping the bits of the n-bit counter. The number of different binary addresses that an n-bit counter can generate is n factorial.
    Type: Application
    Filed: August 21, 2006
    Publication date: December 14, 2006
    Inventors: Oiong Wu, Kwok Chau, Hau-Yung Chen
  • Patent number: 7116718
    Abstract: A method and apparatus is provided for generating various binary addresses for use in decoding MPEG video data. One or more n-bit counters and mutiplexers are used to generate such binary addresses. Different binary addresses can be generated by the same n-bit counter by swapping the bits of the n-bit counter. The number of different binary addresses that an n-bit counter can generate is n factorial.
    Type: Grant
    Filed: September 11, 2002
    Date of Patent: October 3, 2006
    Assignee: NJR Corporation
    Inventors: Qiong Wu, Kwok K. Chau, Hau-Yung Chen
  • Publication number: 20040057522
    Abstract: A method and apparatus is provided for generating various binary addresses for use in decoding MPEG video data. One or more n-bit counters and mutiplexers are used to generate such binary addresses. Different binary addresses can be generated by the same n-bit counter by swapping the bits of the n-bit counter. The number of different binary addresses that an n-bit counter can generate is n factorial.
    Type: Application
    Filed: September 11, 2002
    Publication date: March 25, 2004
    Inventors: Qiong Wu, Kwok K. Chau, Hau-Yung Chen
  • Patent number: 5930499
    Abstract: The invention resides in a computer-aided design system for defining physical placement and floor-planning of electronic circuits on a given substrate. Improve utilization of substrate area is achieved by arranging circuits into structural (e.g., data-path) and non-structural (e.g., non-data-path) zones for effectively segregated chip or board lay-out. Software is provided to receive a netlist file and determine therefrom which components are categorizable within structural portion. Furthermore, software is provided to produce a lay-out file which defines physical placement of the prototype design, wherein structural components are inter-placed with related control components, for example, to provide sliced-structure placement of a semiconductor chip.
    Type: Grant
    Filed: May 20, 1996
    Date of Patent: July 27, 1999
    Assignee: Arcadia Design Systems, Inc.
    Inventors: Yulin Chen, Tsu-Wei Ku, Wei-Kong Chia, Hau-Yung Chen, Rwei-Cheng Lo