Patents by Inventor Hauk Han
Hauk Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200303409Abstract: A semiconductor device includes gate electrodes and interlayer insulating layers that are alternately stacked on a substrate, channel structures spaced apart from each other in a first direction and extending vertically through the gate electrodes and the interlayer insulating layers to the substrate, and a first separation region extending vertically through the gate electrodes and the interlayer insulating layers. Each gate electrode includes a first conductive layer and a second conductive layer, the first conductive layer disposed between the second conductive layer and each of two adjacent interlayer insulating layers. In a first region, between an outermost channel structure and the first separation region, of each gate electrode, the first conductive layer has a decreasing thickness toward the first separation region and the second conductive layer has an increasing thickness toward the first separation region.Type: ApplicationFiled: December 2, 2019Publication date: September 24, 2020Inventors: Taisoo Lim, Kyungwook Park, Keun Lee, Hauk Han
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Patent number: 10734493Abstract: A semiconductor memory device may include a substrate, gate electrode structures stacked on the substrate, insulation patterns between the gate electrode structures, vertical channels penetrating through the gate electrode structures and the insulation patterns, and a data storage pattern. The vertical channels may be electrically connected to the substrate. The data storage pattern may be arranged between the gate electrode structures and the vertical channels. Each of the gate electrode structures may include a barrier film, a metal gate, and a crystal grain boundary plugging layer. The crystal grain boundary plugging layer may be between the barrier film and the metal gate.Type: GrantFiled: July 9, 2018Date of Patent: August 4, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Hauk Han, Je-hyeon Park, Do-hyung Kim, Tae-yong Kim, Keun Lee, Jeong-gil Lee, Hyun-seok Lim
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Publication number: 20190013388Abstract: A semiconductor memory device may include a substrate, gate electrode structures stacked on the substrate, insulation patterns between the gate electrode structures, vertical channels penetrating through the gate electrode structures and the insulation patterns, and a data storage pattern. The vertical channels may be electrically connected to the substrate. The data storage pattern may be arranged between the gate electrode structures and the vertical channels. Each of the gate electrode structures may include a barrier film, a metal gate, and a crystal grain boundary plugging layer. The crystal grain boundary plugging layer may be between the barrier film and the metal gate.Type: ApplicationFiled: July 9, 2018Publication date: January 10, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Hauk Han, Je-Hyeon Park, Do-hyung Kim, Tae-yong Kim, Keun Lee, Jeong-gil Lee, Hyun-seok Lim
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Publication number: 20180358379Abstract: A semiconductor device includes a lower structure including a lower conductor, an upper structure having an opening exposing the lower conductor on the lower structure, and a connection structure filling the opening and connected to the lower conductor. The connection structure includes a first tungsten layer covering an inner surface of the opening and defining a recess region in the opening, and a second tungsten layer filling the recess region on the first tungsten layer. A grain size of the second tungsten layer in an upper portion of the connection structure is greater than a grain size of the second tungsten layer in a lower portion of the connection structure.Type: ApplicationFiled: August 22, 2018Publication date: December 13, 2018Inventors: Hauk HAN, Je-Hyeon PARK, Kihyun YOON, Changwon LEE, HyunSeok LIM, Jooyeon HA
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Patent number: 10079245Abstract: A semiconductor device includes a lower structure including a lower conductor, an upper structure having an opening exposing the lower conductor on the lower structure, and a connection structure filling the opening and connected to the lower conductor. The connection structure includes a first tungsten layer covering an inner surface of the opening and defining a recess region in the opening, and a second tungsten layer filling the recess region on the first tungsten layer. A grain size of the second tungsten layer in an upper portion of the connection structure is greater than a grain size of the second tungsten layer in a lower portion of the connection structure.Type: GrantFiled: August 26, 2016Date of Patent: September 18, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hauk Han, Je-Hyeon Park, Kihyun Yoon, Changwon Lee, HyunSeok Lim, Jooyeon Ha
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Patent number: 10074560Abstract: A method of manufacturing a semiconductor device includes forming an insulating pattern layer on a substrate, conformally forming a first conductive layer with a first thickness on the insulating pattern layer, wet etching the first conductive layer to have a second thickness that is less than the first thickness, and forming a second conductive layer on the first conductive layer after wet etching the first conductive layer. The second conductive layer includes a material that is different from a material included in the first conductive layer.Type: GrantFiled: May 22, 2017Date of Patent: September 11, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Ki-hyun Yoon, Hauk Han, Yeon-sil Sohn, Seul-gi Bae, Hyun-seok Lim
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Patent number: 9997462Abstract: A memory device includes a vertical string of nonvolatile memory cells on a substrate, along with a ground selection transistor extending between the vertical string of nonvolatile memory cells and the substrate. The ground selection transistor can have a current carrying terminal electrically coupled to a channel region of a nonvolatile memory cell in the vertical string of nonvolatile memory cells. The ground selection transistor includes a gate electrode associated with a ground selection line of the memory device. This gate electrode includes: (i) a mask pattern, (ii) a barrier metal layer of a first material extending opposite a sidewall of the mask pattern and (iii) a metal pattern of a second material different from the first material extending between at least a portion of the barrier metal layer and the mask pattern.Type: GrantFiled: April 28, 2017Date of Patent: June 12, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Jooyeon Ha, Jeonggil Lee, Dohyung Kim, Keun Lee, HyunSeok Lim, Hauk Han
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Publication number: 20180122742Abstract: A memory device includes a vertical string of nonvolatile memory cells on a substrate, along with a ground selection transistor extending between the vertical string of nonvolatile memory cells and the substrate. The ground selection transistor can have a current carrying terminal electrically coupled to a channel region of a nonvolatile memory cell in the vertical string of nonvolatile memory cells. The ground selection transistor includes a gate electrode associated with a ground selection line of the memory device. This gate electrode includes: (i) a mask pattern, (ii) a barrier metal layer of a first material extending opposite a sidewall of the mask pattern and (iii) a metal pattern of a second material different from the first material extending between at least a portion of the barrier metal layer and the mask pattern.Type: ApplicationFiled: April 28, 2017Publication date: May 3, 2018Inventors: Jooyeon HA, Jeonggil LEE, Dohyung KIM, Keun LEE, HyunSeok LIM, Hauk HAN
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Patent number: 9953997Abstract: Disclosed is a semiconductor memory device including stacks on a substrate, a vertical channel portion connected to the substrate through each of the stacks, and a separation pattern disposed between the stacks. Each of the stacks may include a plurality of gate electrodes stacked on the substrate and insulating patterns interposed between the gate electrodes. Each of the gate electrodes may include a first metal pattern, which is disposed between the insulating patterns to define a recess region recessed toward the vertical channel portion, and a second metal pattern disposed in the recess region. The first and second metal patterns may contain the same metallic material and may have mean grain sizes different from each other.Type: GrantFiled: August 29, 2016Date of Patent: April 24, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Joyoung Park, Hauk Han, Seok-Won Lee, Jeonggil Lee, Jinwoo Park, Kihyun Yoon, Hyunseok Lim, Jooyeon Ha
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Publication number: 20180090325Abstract: A method of manufacturing a semiconductor device includes forming an insulating pattern layer on a substrate, conformally forming a first conductive layer with a first thickness on the insulating pattern layer, wet etching the first conductive layer to have a second thickness that is less than the first thickness, and forming a second conductive layer on the first conductive layer after wet etching the first conductive layer. The second conductive layer includes a material that is different from a material included in the first conductive layer.Type: ApplicationFiled: May 22, 2017Publication date: March 29, 2018Inventors: Ki-hyun YOON, Hauk HAN, Yeon-sil SOHN, Seul-gi BAE, Hyun-seok LIM
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Patent number: 9865617Abstract: A semiconductor device includes a first interlayer insulating layer and a second interlayer insulating layer, and a horizontal conductive pattern interposed between the first interlayer insulating layer and the second interlayer insulating layer. Vertical structures extend through the first interlayer insulating layer, the second interlayer insulating layer, and the horizontal conductive pattern. Each of the first interlayer insulating layer and the second interlayer insulating layer has regions of different impurity concentrations.Type: GrantFiled: January 10, 2017Date of Patent: January 9, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Hauk Han, Ji Woon Im, Do Hyung Kim, Hyun Seok Lim
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Publication number: 20170330893Abstract: A semiconductor device includes a first interlayer insulating layer and a second interlayer insulating layer, and a horizontal conductive pattern interposed between the first interlayer insulating layer and the second interlayer insulating layer. Vertical structures extend through the first interlayer insulating layer, the second interlayer insulating layer, and the horizontal conductive pattern. Each of the first interlayer insulating layer and the second interlayer insulating layer has regions of different impurity concentrations.Type: ApplicationFiled: January 10, 2017Publication date: November 16, 2017Inventors: HAUK HAN, JI WOON IM, DO HYUNG KIM, HYUN SEOK LIM
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Publication number: 20170062470Abstract: A semiconductor device includes a lower structure including a lower conductor, an upper structure having an opening exposing the lower conductor on the lower structure, and a connection structure filling the opening and connected to the lower conductor. The connection structure includes a first tungsten layer covering an inner surface of the opening and defining a recess region in the opening, and a second tungsten layer filling the recess region on the first tungsten layer. A grain size of the second tungsten layer in an upper portion of the connection structure is greater than a grain size of the second tungsten layer in a lower portion of the connection structure.Type: ApplicationFiled: August 26, 2016Publication date: March 2, 2017Inventors: Hauk HAN, Je-Hyeon PARK, Kihyun YOON, Changwon LEE, HyunSeok LIM, Jooyeon HA
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Publication number: 20170062472Abstract: Disclosed is a semiconductor memory device including stacks on a substrate, a vertical channel portion connected to the substrate through each of the stacks, and a separation pattern disposed between the stacks. Each of the stacks may include a plurality of gate electrodes stacked on the substrate and insulating patterns interposed between the gate electrodes. Each of the gate electrodes may include a first metal pattern, which is disposed between the insulating patterns to define a recess region recessed toward the vertical channel portion, and a second metal pattern disposed in the recess region. The first and second metal patterns may contain the same metallic material and may have mean grain sizes different from each other.Type: ApplicationFiled: August 29, 2016Publication date: March 2, 2017Inventors: Joyoung PARK, HAUK HAN, SEOK-WON LEE, JEONGGIL LEE, JINWOO PARK, KlHYUN YOON, HYUNSEOK LIM, JOOYEON HA
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Publication number: 20160329342Abstract: A semiconductor device includes a charge storage pattern on a substrate, a blocking insulating pattern on the charge storage pattern, and a control gate structure on the blocking insulating pattern, the control gate structure having a metal electrode pattern, and an oxidation prevention pattern on the metal electrode pattern, the oxidation prevention pattern including a metallic nitride.Type: ApplicationFiled: April 12, 2016Publication date: November 10, 2016Inventors: Hauk HAN, Yeon-Sil SOHN
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Patent number: 9299826Abstract: A memory device includes a gate structure, a contact plug, and a spacer. The gate structure includes first and second conductive layer patterns sequentially stacked on a substrate. The contact plug passes through the second conductive layer pattern, and a sidewall of the contact plug directly contacts at least a portion of the second conductive layer pattern. The spacer surrounds a portion of the sidewall of the contact plug and contacting the gate structure.Type: GrantFiled: March 11, 2014Date of Patent: March 29, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hauk Han, Il-Woo Kim, Jeong-Gil Lee, Yong-Il Kwon, Myoung-Bum Lee
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Patent number: 9245899Abstract: A semiconductor device includes a lower insulating pattern on a semiconductor substrate, a lower gate pattern on the lower insulating pattern and formed of a doped polysilicon layer, a residual insulating pattern with an opening exposing a portion of a top surface of the lower gate pattern, an upper gate pattern on the residual insulating pattern, the upper gate pattern filling the opening, and a diffusion barrier pattern in contact with the portion of the top surface of the lower gate pattern and extending between the residual insulating pattern and the upper gate pattern.Type: GrantFiled: June 16, 2015Date of Patent: January 26, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hauk Han, Yong-IL Kwon, JungSuk Oh, Tae sun Ryu, Jeonggil Lee
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Publication number: 20150311298Abstract: A semiconductor device includes a lower insulating pattern on a semiconductor substrate, a lower gate pattern on the lower insulating pattern and formed of a doped polysilicon layer, a residual insulating pattern with an opening exposing a portion of a top surface of the lower gate pattern, an upper gate pattern on the residual insulating pattern, the upper gate pattern filling the opening, and a diffusion barrier pattern in contact with the portion of the top surface of the lower gate pattern and extending between the residual insulating pattern and the upper gate pattern.Type: ApplicationFiled: June 16, 2015Publication date: October 29, 2015Inventors: Hauk Han, Yong-IL Kwon, JungSuk Oh, Tae sun Ryu, Jeonggil Lee
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Patent number: 9082653Abstract: A semiconductor device includes a lower insulating pattern on a semiconductor substrate, a lower gate pattern on the lower insulating pattern and formed of a doped polysilicon layer, a residual insulating pattern with an opening exposing a portion of a top surface of the lower gate pattern, an upper gate pattern on the residual insulating pattern, the upper gate pattern filling the opening, and a diffusion barrier pattern in contact with the portion of the top surface of the lower gate pattern and extending between the residual insulating pattern and the upper gate pattern.Type: GrantFiled: December 5, 2014Date of Patent: July 14, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Hauk Han, Yong-IL Kwon, JungSuk Oh, Tae sun Ryu, Jeonggil Lee
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Publication number: 20150137259Abstract: A semiconductor device includes a substrate including a conductive region, an insulating layer disposed on the substrate and including an opening exposing the conductive region, and a conductive layer buried within the opening and including a first region disposed on inner side walls of the opening and a second region disposed within the first region. The first region includes a plurality of first crystal grains and the second region includes a plurality of second crystal grains. The pluralities of first and second crystal grains are separated from each other at a boundary formed between the first and second regions.Type: ApplicationFiled: August 7, 2014Publication date: May 21, 2015Inventors: Hauk HAN, Yu Min KIM, Ki Hyun YOON, Myoung Bum LEE, Chang Won LEE, Joo Yeon HA