Abstract: A method of fabricating a double gate, FINFET device structure in a silicon on insulator layer, in which the channel region formed in the SOI layer is defined with a narrowed, or necked shape, and wherein a composite insulator spacer is formed on the sides of the device structure, has been developed. A FINFET device structure shape is formed in an SOI layer via anisotropic RIE procedures, followed by a growth of a silicon dioxide gate insulator layer on the sides of the FINFET device structure shape. A gate structure is fabricated traversing the device structure and overlying the silicon dioxide gate insulator layer located on both sides of the narrowest portion of channel region. After formation of a source/drain region in wider, non-channel regions of the FINFET device structure shape, composite insulator spacers are formed on the sides of the FINFET shape and on the sides of the gate structure.

Abstract: A method of fabricating a double gate, FINFET device structure in a silicon on insulator layer, in which the channel region formed in the SOI layer is defined with a narrowed, or necked shape, and wherein a composite insulator spacer is formed on the sides of the device structure, has been developed. A FINFET device structure shape is formed in an SOI layer via anisotropic RIE procedures, followed by a growth of a silicon dioxide gate insulator layer on the sides of the FINFET device structure shape. A gate structure is fabricated traversing the device structure and overlying the silicon dioxide gate insulator layer located on both sides of the narrowest portion of channel region. After formation of a source/drain region in wider, non-channel regions of the FINFET device structure shape, composite insulator spacers are formed on the sides of the FINFET shape and on the sides of the gate structure.

Abstract: A method of fabricating a double gate, FINFET device structure in a silicon on insulator layer, in which the channel region formed in the SOI layer is defined with a narrowed, or necked shape, and wherein a composite insulator spacer is formed on the sides of the device structure, has been developed. A FINFET device structure shape is formed in an SOI layer via anisotropic RIE procedures, followed by a growth of a silicon dioxide gate insulator layer on the sides of the FINFET device structure shape. A gate structure is fabricated traversing the device structure and overlying the silicon dioxide gate insulator layer located on both sides of the narrowest portion of channel region. After formation of a source/drain region in wider, non-channel regions of the FINFET device structure shape, composite insulator spacers are formed on the sides of the FINFET shape and on the sides of the gate structure.

Abstract: A method of forming a composite gate structure for a planar MOSFET device, as well as for vertical, double gate, FINFET device, has been developed. The method features a composite gate structure comprised of an overlying silicon gate structure shape, and an underlying titanium nitride gate structure shape. The titanium nitride component allows a lower work function, and thus lower device operating voltages to be realized when compared to counterpart gate structures formed with only polysilicon. A novel, two step gate structure definition procedure, featuring an anisotropic first etch procedure for definition of the polysilicon gate structure shape, followed by a wet or dry isotopic second etch procedure for definition of the titanium nitride gate structure shape, is employed.

Abstract: A silicon-on-insulator substrate comprises a first silicon substrate having a first crystal orientation, said first substrate having a first polished surface and a first wafer notch; a second silicon substrate having a second crystal orientation different from the first crystal orientation of the first silicon substrate, said second substrate having a second polished surface and a second wafer notch; and the first polished surface of the first silicon substrate being bonded to the second polished surface of the second silicon substrates.

Abstract: A new silicon structure is provided. Under a first embodiment of the invention, a first silicon substrate having a <100> crystallographic orientation is bonded to the surface of a second silicon substrate having a <110> crystallographic orientation, the wafer alignment notch of the first and the second silicon substrates are aligned with each other. Under a first embodiment of the invention, a first silicon substrate having a <100> crystallographic orientation is bonded to the surface of a second silicon substrate having a <110> crystallographic orientation, the wafer alignment notch of the first and the second silicon substrates are not aligned with each other.

Abstract: A new silicon structure is provided. Under a first embodiment of the invention, a first silicon substrate having a <100> crystallographic orientation is bonded to the surface of a second silicon substrate having a <110> crystallographic orientation, the wafer alignment notch of the first and the second silicon substrates are aligned with each other. Under a first embodiment of the invention, a first silicon substrate having a <100> crystallographic orientation is bonded to the surface of a second silicon substrate having a <110> crystallographic orientation, the wafer alignment notch of the first and the second silicon substrates are not aligned with each other.

Abstract: A method of forming a composite gate structure for a planar MOSFET device, as well as for vertical, double gate, FINFET device, has been developed. The method features a composite gate structure comprised of an overlying silicon gate structure shape, and an underlying titanium nitride gate structure shape. The titanium nitride component allows a lower work function, and thus lower device operating voltages to be realized when compared to counterpart gate structures formed with only polysilicon. A novel, two step gate structure definition procedure, featuring an anisotropic first etch procedure for definition of the polysilicon gate structure shape, followed by a wet or dry isotropic second etch procedure for definition of the titanium nitride gate structure shape, is employed.