Abstract: An apparatus for and method of generating a clock signal having a desired frequency that is derived from a clock source having any arbitrary,frequency. The mechanism of the present invention generates an average rate, very close to the optimal rate desired, by ‘swallowing’ or absorbing clock cycles of the available frequency source. Precise timing is achieved by adding correcting time intervals, which are based on counting pulses from the higher rate clock source. The clock frequency generator comprises a standby mode state machine and a jitter calculation processor. Timing calculations are performed by the jitter calculation processor and the standby mode state machine functions to generate the desired standby mode clock frequency. The state machine utilizes counters to track the number of cycles of the available clock and the number of generated cycles of the standby clock.