Patents by Inventor Haw-Chuan Wu

Haw-Chuan Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor structure, integrated circuit device, and method of forming semiconductor structure
    Patent number: 11145604
    Abstract: A semiconductor structure, integrated circuit device, and method of forming semiconductor structure are provided. In various embodiments, the semiconductor structure includes a substrate containing a high topography region and a low topography region, an outer protection wall on an outer peripheral portion of the high topography region next to the low topography region, and an anti-reflective coating over the outer protection wall, the high topography region, and the low topography region.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: October 12, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Hsien Ma, Haw-Chuan Wu, Shih-Hao Tsai, Yu-Chuan Lin
  • SEMICONDUCTOR STRUCTURE, INTEGRATED CIRCUIT DEVICE, AND METHOD OF FORMING SEMICONDUCTOR STRUCTURE
    Publication number: 20200152583
    Abstract: A semiconductor structure, integrated circuit device, and method of forming semiconductor structure are provided. In various embodiments, the semiconductor structure includes a substrate containing a high topography region and a low topography region, an outer protection wall on an outer peripheral portion of the high topography region next to the low topography region, and an anti-reflective coating over the outer protection wall, the high topography region, and the low topography region.
    Type: Application
    Filed: January 13, 2020
    Publication date: May 14, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Hsien MA, Haw-Chuan WU, Shih-Hao TSAI, Yu-Chuan LIN
  • Semiconductor structure, integrated circuit device, and method of forming semiconductor structure
    Patent number: 10535613
    Abstract: A semiconductor structure, integrated circuit device, and method of forming semiconductor structure are provided. In various embodiments, the semiconductor structure includes a substrate containing a high topography region and a low topography region, an outer protection wall on an outer peripheral portion of the high topography region next to the low topography region, and an anti-reflective coating over the outer protection wall, the high topography region, and the low topography region.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: January 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Hsien Ma, Haw-Chuan Wu, Shih-Hao Tsai, Yu-Chuan Lin
  • SEMICONDUCTOR STRUCTURE, INTEGRATED CIRCUIT DEVICE, AND METHOD OF FORMING SEMICONDUCTOR STRUCTURE
    Publication number: 20180166395
    Abstract: A semiconductor structure, integrated circuit device, and method of forming semiconductor structure are provided. In various embodiments, the semiconductor structure includes a substrate containing a high topography region and a low topography region, an outer protection wall on an outer peripheral portion of the high topography region next to the low topography region, and an anti-reflective coating over the outer protection wall, the high topography region, and the low topography region.
    Type: Application
    Filed: February 9, 2018
    Publication date: June 14, 2018
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Hsien MA, Haw-Chuan WU, Shih-Hao TSAI, Yu-Chuan LIN
  • Semiconductor structure, integrated circuit device, and method of forming semiconductor structure
    Patent number: 9893019
    Abstract: A semiconductor structure, integrated circuit device, and method of forming semiconductor structure are provided. In various embodiments, the semiconductor structure includes a substrate containing a high topography region and a low topography region, an outer protection wall on an outer peripheral portion of the high topography region next to the low topography region, and an anti-reflective coating over the outer protection wall, the high topography region, and the low topography region.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: February 13, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Hsien Ma, Haw-Chuan Wu, Shih-Hao Tsai, Yu-Chuan Lin
  • SEMICONDUCTOR STRUCTURE, INTEGRATED CIRCUIT DEVICE, AND METHOD OF FORMING SEMICONDUCTOR STRUCTURE
    Publication number: 20170077224
    Abstract: A semiconductor structure, integrated circuit device, and method of forming semiconductor structure are provided. In various embodiments, the semiconductor structure includes a substrate containing a high topography region and a low topography region, an outer protection wall on an outer peripheral portion of the high topography region next to the low topography region, and an anti-reflective coating over the outer protection wall, the high topography region, and the low topography region.
    Type: Application
    Filed: September 15, 2015
    Publication date: March 16, 2017
    Inventors: Shih-Hsien MA, Haw-Chuan WU, Shih-Hao TSAI, Yu-Chuan LIN
  • Split gate field effect transistor device with aligned gate electrode sidewalls
    Publication number: 20070063250
    Abstract: A split gate field effect transistor is fabricated with a sidewall of a control gate electrode aligned with a sidewall of a floating gate electrode. The aligned sidewalls are on a side of the split gate field effect transistor device opposite the control gate electrode channel of the split gate field effect transistor device. The aligned sidewalls provide for enhanced performance of the split gate field effect transistor device.
    Type: Application
    Filed: September 20, 2005
    Publication date: March 22, 2007
    Inventors: Haw-Chuan Wu, Wong-Chu Chu, Dah-Chuen Ho, Kuang Yang
  • Method for integrated manufacturing of split gate flash memory with high voltage MOSFETS
    Patent number: 6998304
    Abstract: A method for integrated processing of a high Voltage MOSFET device and a split gate MOSFET device whereby a novel method is provided to form the split gate device and the high voltage MOSFET device in parallel processing steps including an oxide formation step whereby an oxide spacer layer in a split gate device is formed using about the same overall thermal budget while forming in parallel a thick gate oxide for a an embedded high voltage MOSFET device.
    Type: Grant
    Filed: March 1, 2004
    Date of Patent: February 14, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Haw-Chuan Wu, Jiann-Tyng Tzeng, David Ho
  • Method for integrated manufacturing of split gate flash memory with high voltage MOSFETS
    Publication number: 20050191800
    Abstract: A method for integrated processing of a high Voltage MOSFET device and a split gate MOSFET device whereby a novel method is provided to form the split gate device and the high voltage MOSFET device in parallel processing steps including an oxide formation step whereby an oxide spacer layer in a split gate device is formed using about the same overall thermal budget while forming in parallel a thick gate oxide for a an embedded high voltage MSOFET device.
    Type: Application
    Filed: March 1, 2004
    Publication date: September 1, 2005
    Inventors: Haw-Chuan Wu, Jiann-Tyng Tzeng, David Ho