Patents by Inventor Hayao Ohzu
Hayao Ohzu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6747699Abstract: A solid state image pickup device includes light-receiving circuitry having a plurality of light-receiving cells arranged in a matrix. Apparatus is provided for reading and storing electrical signals output by the light-receiving circuitry, and includes (1) a first memory for reading bright signals out of the light-receiving cells arranged in a row for storing the bright signals for a horizontal scanning period, (2) a second memory for reading dark signals out of the light-receiving cells arranged in the row for storing the dark signal for the horizontal scanning period, and (3) a readout circuit for reading the bright and dark signals stored in the first and second memories simultaneously. A removing circuit is provided for removing fixed pattern noise by simultaneously processing the bright and dark current signals read out from the first and second memories. Preferably, this removing circuit comprises a differential amplifier.Type: GrantFiled: March 18, 1998Date of Patent: June 8, 2004Assignee: Canon Kabushiki KaishaInventors: Hayao Ohzu, Toshiji Suzuki, Akira Ishizaki, Seiji Hashimoto, Tadanori Harada, Tsuneo Suzuki
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Publication number: 20040046879Abstract: A solid state imag pickup device included light-receiving circuitry having a plurality of light-receiving cells arranged in a matrix. Apparatus is provided for reading and storing electrical signals output by the light-receiving circuitry, and includes (1) a first memory for reading bright signals out of the light-receiving cells arranged in a row for storing the bright signals for a horizontal scanning period, (2) a second memory for reading dark signals out of the light-receiving cells arranged in the row for storing the dark signal for the horizontal scanning period, and (3) a readout circuit for reading the bright and dark signals stored in the first and second memories simultaneously. A removing circuit is provided for removing fixed pattern noise by simultaneously processing the bright and dark current signals read out from the first and second memories. Preferably, this removing circuit comprises a differential amplifier.Type: ApplicationFiled: September 8, 2003Publication date: March 11, 2004Applicant: CANNON KABUSHIKI KAISHAInventors: Hayao Ohzu, Toshiji Suzuki, Akira Ishizaki, Seiji Hashimoto, Tadanori Harada, Tsuneo Suzuki
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Publication number: 20020167601Abstract: A solid state image pickup device includes light-receiving circuitry having a plurality of light-receiving cells arranged in a matrix. Apparatus is provided for reading and storing electrical signals output by the light-receiving circuitry, and includes (1) a first memory for reading bright signals out of the light-receiving cells arranged in a row for storing the bright signals for a horizontal scanning period, (2) a second memory for reading dark signals out of the light-receiving cells arranged in the row for storing the dark signal for the horizontal scanning period, and (3) a readout circuit for reading the bright and dark signals stored in the first and second memories simultaneously. A removing circuit is provided for removing fixed pattern noise by simultaneously processing the bright and dark current signals read out from the first and second memories. Preferably, this removing circuit comprises a differential amplifier.Type: ApplicationFiled: April 16, 2002Publication date: November 14, 2002Applicant: Canon Kabushiki KaishaInventors: Hayao Ohzu, Toshiji Suzuki, Akira Ishizaki, Seiji Hashimoto, Tadanori Harada, Tsuneo Suzuki
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Patent number: 6373099Abstract: A semiconductor device including: an insulated gate type transistor having a columnar semiconductor region formed on the main side of a semiconductor substrate, a gate electrode formed on the side surface of the columnar semiconductor region while interposing a gate insulating film and main electrode regions respectively formed on and formed below the columnar semiconductor region; and a memory element which is formed on the upper main electrode region and which can be broken electrically.Type: GrantFiled: February 18, 1999Date of Patent: April 16, 2002Assignee: Canon Kabushiki KaishaInventors: Shin Kikuchi, Hayao Ohzu, Shunsuke Inoue, Yoshio Nakamura, Takeshi Ichikawa, Osamu Ikeda
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Publication number: 20020001033Abstract: A solid state image pickup device includes light-receiving circuitry having a plurality of light-receiving cells arranged in a matrix. Apparatus is provided for reading and storing electrical signals output by the light-receiving circuitry, and includes (1) a first memory for reading bright signals out of the light-receiving cells arranged in a row for storing the bright signals for a horizontal scanning period, (2) a second memory for reading dark signals out of the light-receiving cells arranged in the row for storing the dark signal for the horizontal scanning period, and (3) a readout circuit for reading the bright and dark signals stored in the first and second memories simultaneously. A removing circuit is provided for removing fixed pattern noise by simultaneously processing the bright and dark current signals read out from the first and second memories. Preferably, this removing circuit comprises a differential amplifier.Type: ApplicationFiled: March 18, 1998Publication date: January 3, 2002Inventors: HAYAO OHZU, TOSHIJI SUZUKI, AKIRA ISHIZAKI, SEIJI HASHIMOTO, TADANORI HARADA, TSUNEO SUZUKI
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Patent number: 6097067Abstract: In a semiconductor apparatus comprises a signal input portion having an amplifying circuit including one, two or more insulating gate type transistors (MIS Tr), one MIS Tr or at least one (M1) of the two or more MIS Trs of the signal input portion is an MIS Tr of one conductivity channel type. The MIS Tr (M1) of the one conductivity channel type is formed in a semiconductor region which is electrically isolated from the other MIS Tr (M3) of one conductivity channel type provided for a circuit portion other than the signal input portion, so that an input threshold level of the signal amplifying circuit is made coincide with a DC level of the input signal, thereby preventing an erroneous operation.Type: GrantFiled: April 3, 1997Date of Patent: August 1, 2000Assignee: Canon Kabushiki KaishaInventors: Akihiro Ouchi, Hayao Ohzu, Yukihiko Sakashita
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Patent number: 5918115Abstract: A semiconductor device including: an insulated gate type transistor having a columnar semiconductor region formed on the main side of a semiconductor substrate, a gate electrode formed on the side surface of the columnar semiconductor region while interposing a gate insulating film and main electrode regions respectively formed on and formed below the columnar semiconductor region; and a memory element which is formed on the upper main electrode region and which can be broken electrically.Type: GrantFiled: July 29, 1997Date of Patent: June 29, 1999Assignee: Canon Kabushiki KaishaInventors: Shin Kikuchi, Mamoru Miyawaki, Genzo Monma, Hayao Ohzu, Shunsuke Inoue, Yoshio Nakamura, Takeshi Ichikawa, Osamu Ikeda, Tetsunobu Kohchi
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Patent number: 5900884Abstract: A parametric curve generating device for developing a Bezier curve is provided. The device is capable of executing a high speed division operation with a limited magnitude of hardware scale. Adders perform calculations that are stored in registers. Convergence discrimination circuits discriminate whether data stored in the registers converge. Subsequent processing varies depending on the discrimination result. A stack memory is used to store data from the registers.Type: GrantFiled: May 29, 1996Date of Patent: May 4, 1999Assignee: Canon Kabushiki KaishaInventors: Toshiaki Minami, Tatsuhiko Yamazaki, Hayao Ohzu, Yuji Hara
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Patent number: 5872574Abstract: A minimum coordinate value at least in one direction of a parameter data group including a start point and an end point of a stroke is detected and outline coordinates are generated from the parameter data group by an outline coordinate generator and a minimum coordinate detector. An outline data generator stores range data indicative of a painting range into a predetermined address in an outline buffer on the basis of the outline coordinates and the minimum coordinate value or the maximum coordinate value. An address generator generates a drawing start address and an end address in a bit map memory in accordance with a value based on the minimum coordinate value and the predetermined address and with the range data. A painter paints by writing the same value into all data between the drawing start address and end address in the bit map memory, thereby generating a character pattern at a high speed by a buffer memory of a small capacity.Type: GrantFiled: May 30, 1997Date of Patent: February 16, 1999Assignee: Canon Kabushiki KaishaInventors: Yuji Hara, Tatsuhiko Yamazaki, Hayao Ohzu, Toshiaki Minami
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Patent number: 5864495Abstract: An arithmetic processing apparatus or circuit for performing charge redistribution by one or more capacitances connected to an input portion of each comparator are realized with improved arithmetic accuracy as suppressing dispersion and errors of gains of signals input into comparators, in such an arrangement that as the arithmetic processing apparatus is arranged to have a plurality of comparators, each having one or more capacitances connected to the input portion thereof, a sum of the capacitors connected to the input portions of each comparators 71 (or 72), C.sub.11 +. . .+C.sub.1n (or C.sub.81 +. . .+C.sub.8m), is substantially equalized among the plurality of comparators, or a ratio of the sum of the capacitors connected to the input portion of each comparator 71 (or 72), C.sub.11 +. . .+C.sub.1n (or C.sub.81 +. . .+C.sub.8m), and input capacitance C.sub.p1 (or C.sub.p2) of the comparator is substantially equalized among the comparators.Type: GrantFiled: January 25, 1996Date of Patent: January 26, 1999Assignee: Canon Kabushiki KaishaInventors: Yukihiko Sakashita, Hayao Ohzu, Akihiro Ouchi
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Patent number: 5835045Abstract: A reduction in circuit size, an increase in operation speed, and a reduction in power consumption can be attained by a semiconductor device, in which capacitors are connected to multiple input terminals through switch, one terminal of each capacitance is commonly connected, and the common connection terminal is connected to a sense amplifier, including a reset at a floating point which is the contact between the common connection terminal of the capacitors and the input of the sense amplifier. In addition, an increase in yield can be realized by reducing the manufacturing cost.Type: GrantFiled: October 26, 1995Date of Patent: November 10, 1998Assignee: Canon Kabushiki KaishaInventors: Katsuhisa Ogawa, Mamoru Miyawaki, Hayao Ohzu, Yukihiko Sakashita, Tetsunobu Kochi, Akihiro Ouchi
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Patent number: 5771070Abstract: A solid state image pickup apparatus for removing noise includes a plurality of photoelectric transducer cells, and first and second switch circuitry. Signal readout lines are provided for reading out signals from the plurality of transducer cells. A plurality of first capacitors, each connected to one of the signal readout lines through the first switch circuitry, are provided for selectively storing first signals read out through the signal lines and the first switch circuitry after a predetermined accumulation period. A plurality of second capacitors, each connected to one of the signal read out lines through the second switch circuitry, are provided for selectively storing second signals corresponding to dark current signals read out through the signal read out lines and the second switch circuitry.Type: GrantFiled: August 29, 1996Date of Patent: June 23, 1998Assignee: Canon Kabushiki KaishaInventors: Hayao Ohzu, Toshiji Suzuki, Akira Ishizaki, Seiji Hashimoto, Tadanori Harada, Tsuneo Suzuki
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Patent number: 5737016Abstract: Solid state image pickup apparatus for removing noise includes a plurality of photoelectric transducer elements for converting incident light into electrical signals, each of the transducer elements having a signal fluctuation. Control circuitry is provided having a first mode for reading out from each transducer element a first signal corresponding to a signal component and a noise component caused by the fluctuation. The control circuitry has a second mode for reading out from each transducer element a second signal corresponding to the noise component caused by the fluctuation, the first and second signals being read out in the same manner from each transducer element. Amplification circuitry is provided for amplifying the first and second signals, the amplification circuitry including a plurality of amplifiers each amplifier being coupled to a respective one of the plurality of transducer elements.Type: GrantFiled: August 7, 1995Date of Patent: April 7, 1998Assignee: Canon Kabushiki KaishaInventors: Hayao Ohzu, Toshiji Suzuki, Akira Ishizaki, Seiji Hashimoto, Tadanori Harada, Tsuneo Suzuki
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Patent number: 5665630Abstract: A semiconductor device has a device region, and a device separation region formed on a semiconductor substrate doped with impurities. And, the device separation region has a metal wiring formed on the surface of the device region or the back surface of the substrate. An aluminum region extending in the longitudinal direction connected to the metal wiring is formed within the device separation region.Type: GrantFiled: November 16, 1994Date of Patent: September 9, 1997Assignee: Canon Kabushiki KaishaInventors: Keiji Ishizuka, Yuzo Kataoka, Toshihiko Ichise, Hidekazu Takahashi, Hayao Ohzu
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Patent number: 5598037Abstract: A semiconductor device including: an insulated gate type transistor having a columnar semiconductor region formed on the main side of a semiconductor substrate, a gate electrode formed on the side surface of the columnar semiconductor region while interposing a gate insulating film and main electrode regions respectively formed on and formed below the columnar semiconductor region; and a memory element which is formed on the upper main electrode region and which can be broken electrically.Type: GrantFiled: March 15, 1995Date of Patent: January 28, 1997Assignee: Canon Kabushiki KaishaInventors: Shin Kikuchi, Mamoru Miyawaki, Genzo Monma, Hayao Ohzu, Shunsuke Inoue, Yoshio Nakamura, Takeshi Ichikawa, Osamu Ikeda, Tetsunobu Kohchi
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Patent number: 5583075Abstract: There is provided a semiconductor device with very small functional elements, which can be constructed by necessary minimum components without any unnecessary surface area, thus being capable of significantly reducing the layout area and adapted for achieving a fine geometry and a high level of integration. The semiconductor device is provided with a first semiconductor area of a first conductive type (for example a p.sup.- well) and a second semiconductor area formed on or under the first semiconductor area and having a second conductive type different from the first conductive type (for example a source or drain area), in which an electrode electrically connected to the first semiconductor area is formed through the second semiconductor area, and the first and second semiconductor areas are shortcircuited by the above-mentioned electrode.Type: GrantFiled: December 5, 1994Date of Patent: December 10, 1996Assignee: Canon Kabushiki KaishaInventors: Hayao Ohzu, Tetsunobu Kochi
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Patent number: 5506430Abstract: A solid state image pick-up device has a first pixel for outputting a first color signal and a second pixel for outputting a second color signal different from the first color signal. The first and second pixels have semiconductor junctions between the first semiconductor region and the second semiconductor region, respectively, with different junction capacities from each other.Type: GrantFiled: May 8, 1995Date of Patent: April 9, 1996Assignee: Canon Kabushiki KaishaInventor: Hayao Ohzu
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Patent number: 5466961Abstract: A semiconductor device including: an insulated gate type transistor having a columnar semiconductor region formed on the main side of a semiconductor substrate, a gate electrode formed on the side surface of the columnar semiconductor region while interposing a gate insulating film and main electrode regions respectively formed on and formed below the columnar semiconductor region; and a memory element which is formed on the upper main electrode region and which can be broken electrically.Type: GrantFiled: April 22, 1992Date of Patent: November 14, 1995Assignee: Canon Kabushiki KaishaInventors: Shin Kikuchi, Mamoru Miyawaki, Genzo Monma, Hayao Ohzu, Shunsuke Inoue, Yoshio Nakamura, Takeshi Ichikawa, Osamu Ikeda, Tetsunobu Kohchi
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Patent number: 5378914Abstract: There is provided a semiconductor device with very small functional elements, which can be constructed by necessary minimum components without any unnecessary surface area, thus being capable of significantly reducing the layout area and adapted for achieving a fine geometry and a high level of integration. The semiconductor device is provided with a first semiconductor area of a first conductive type (for example a p.sup.- well) and a second semiconductor area formed on or under the first semiconductor area and having a second conductive type different from the first conductive type (for example a source or drain area), in which an electrode electrically connected to the first semiconductor area is formed through the second semiconductor area, and the first and second semiconductor areas are shortcircuited by the above-mentioned electrode.Type: GrantFiled: December 24, 1992Date of Patent: January 3, 1995Assignee: Canon Kabushiki KaishaInventors: Hayao Ohzu, Tetsunobu Kochi
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Patent number: 5331421Abstract: A solid state image pickup device includes light-receiving circuitry having a plurality of light-receiving cells arranged in a matrix. Apparatus is provided for reading and storing electrical signals output by the light-receiving circuitry, and includes (1) a first memory for reading bright signals out of the light-receiving cells arranged in a row for storing the bright signals for a horizontal scanning period, (2) a second memory for reading dark signals out of the light-receiving cells arranged in the row for storing the dark signal for the horizontal scanning period, and (3) a readout circuit for reading the bright and dark signals stored in the first and second memories simultaneously. A removing circuit is provided for removing fixed pattern noise by simultaneously processing the bright and dark current signals read out from the first and second memories. Preferably, this removing circuit comprises a differential amplifier.Type: GrantFiled: June 13, 1990Date of Patent: July 19, 1994Assignee: Canon Kabushiki KaishaInventors: Hayao Ohzu, Toshiji Suzuki, Akira Ishizaki