Patents by Inventor Hayashi Mitsuaki

Hayashi Mitsuaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor memory device
    Patent number: 7580316
    Abstract: Subarrays, which constitute a memory cell array, each include a bit line driving transistor having a drain connected to a bit line, a source is connected to an interconnection having a power supply potential, and a gate is connected to a sub-bit line. The plurality of memory cells are each provided in such away that a gate is connected to a word line, a source is grounded, and whether a drain is connected to the sub-bit line or not is selected in correspondence to data to be stored. Transmission transistors each have a gate connected to the bit line, a source connected to a loading transistor section, and a drain connected to the sub-bit line.
    Type: Grant
    Filed: May 12, 2008
    Date of Patent: August 25, 2009
    Assignee: Panasonics Corporation
    Inventors: Hayashi Mitsuaki, Shuji Nakaya, Wataru Abe
  • Semiconductor memory device
    Patent number: 7567480
    Abstract: Subarrays, which constitute a memory cell array, each include a bit line driving transistor having a drain connected to a bit line, a source is connected to an interconnection having a power supply potential, and a gate is connected to a sub-bit line. The plurality of memory cells are each provided in such away that a gate is connected to a word line, a source is grounded, and whether a drain is connected to the sub-bit line or not is selected in correspondence to data to be stored. Transmission transistors each have a gate connected to the bit line, a source connected to a loading transistor section, and a drain connected to the sub-bit line.
    Type: Grant
    Filed: May 12, 2008
    Date of Patent: July 28, 2009
    Assignee: Panasonic Corporation
    Inventors: Hayashi Mitsuaki, Shuji Nakaya, Wataru Abe
  • SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20080291714
    Abstract: Subarrays, which constitute a memory cell array, each include a bit line driving transistor having a drain connected to a bit line, a source is connected to an interconnection having a power supply potential, and a gate is connected to a sub-bit line. The plurality of memory cells are each provided in such away that a gate is connected to a word line, a source is grounded, and whether a drain is connected to the sub-bit line or not is selected in correspondence to data to be stored. Transmission transistors each have a gate connected to the bit line, a source connected to a loading transistor section, and a drain connected to the sub-bit line.
    Type: Application
    Filed: May 12, 2008
    Publication date: November 27, 2008
    Applicant: MATSUSHITA ELECTRONIC INDUSTRIAL CO., LTD.
    Inventors: Hayashi Mitsuaki, Shuji Nakaya, Wataru Abe
  • Semiconductor memory device
    Publication number: 20060239105
    Abstract: Subarrays, which constitute a memory cell array, each include a bit line driving transistor having a drain connected to a bit line, a source is connected to an interconnection having a power supply potential, and a gate is connected to a sub-bit line. The plurality of memory cells are each provided in such away that a gate is connected to a word line, a source is grounded, and whether a drain is connected to the sub-bit line or not is selected in correspondence to data to be stored. Transmission transistors each have a gate connected to the bit line, a source connected to a loading transistor section, and a drain connected to the sub-bit line.
    Type: Application
    Filed: April 18, 2006
    Publication date: October 26, 2006
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Hayashi Mitsuaki, Shuji Nakaya, Wataru Abe