Abstract: A method for manufacturing a semiconductor device includes the step of polishing a conductive film formed over a semiconductor substrate. The conductive film is formed by a barrier film that is in contact with second and third interlayer insulating films, and a copper film that is in contact with the barrier film. A polishing surface of a second polishing pad for polishing and removing the barrier film and the third interlayer insulating film has a lower pore area ratio than a polishing surface of a first polishing pad for polishing and removing the copper film.

Abstract: A method for manufacturing a semiconductor device includes the step of polishing a conductive film formed over a semiconductor substrate. The conductive film is formed by a barrier film that is in contact with second and third interlayer insulating films, and a copper film that is in contact with the barrier film. A polishing surface of a second polishing pad for polishing and removing the barrier film and the third interlayer insulating film has a lower pore area ratio than a polishing surface of a first polishing pad for polishing and removing the copper film.

Abstract: An electronic device includes: a first substrate; and a second substrate on which the first substrate is mounted and which is electrically connected to the first substrate in at least one predetermined area. The predetermined area includes at least two through vias running through the first substrate, and an interconnect provided in the second substrate. The at least two through vias are electrically connected together via the interconnect.

Abstract: A semiconductor device includes a first interlayer insulating film, and a plurality of first interconnects formed in the first interlayer insulating film. A void is selectively formed between adjacent ones of the plurality of first interconnects in the first interlayer insulating film, and a cap insulating film is formed in a region located over the void and between the interconnects. Respective widths of a lower end and an upper end of the void are substantially the same as a gap between the interconnects located adjacent to the void, and the lower end of the void is located lower than lower ends of the first interconnects located adjacent to the void.

Abstract: A semiconductor device includes low concentration source/drain regions and high concentration source/drain regions each being formed in a semiconductor substrate, a gate insulation film formed on part of the semiconductor substrate located between the low concentration source/drain regions when viewed from the top and a gate electrode formed of metal silicide on the gate insulation film. A gate length of upper part of the gate electrode is larger than a gate length of other part of the gate electrode.