Patents by Inventor Hayato Nasu
Hayato Nasu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10777599Abstract: According to one embodiment, the interconnect layers include a first interconnect layer and a second interconnect layer. The second interconnect layer is provided on the first interconnect layer. The insulating layer is provided between the plurality of interconnect layers. The barrier metal film is provided at a surface of the first interconnect layer but not provided at a surface of the second interconnect layer. The plugs connect the first interconnect layer and the second interconnect layer, and are provided between the first interconnect layer and the second interconnect layer. The plugs are arranged at a spacing of 200 ?m or less along a longitudinal direction of the second interconnect layer.Type: GrantFiled: February 13, 2019Date of Patent: September 15, 2020Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventors: Hayato Nasu, Yasushi Itabashi
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Publication number: 20200091216Abstract: According to one embodiment, the interconnect layers include a first interconnect layer and a second interconnect layer. The second interconnect layer is provided on the first interconnect layer. The insulating layer is provided between the plurality of interconnect layers. The barrier metal film is provided at a surface of the first interconnect layer but not provided at a surface of the second interconnect layer. The plugs connect the first interconnect layer and the second interconnect layer, and are provided between the first interconnect layer and the second interconnect layer. The plugs are arranged at a spacing of 200 ?m or less along a longitudinal direction of the second interconnect layer.Type: ApplicationFiled: February 13, 2019Publication date: March 19, 2020Inventors: Hayato Nasu, Yasushi Itabashi
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Patent number: 8133813Abstract: A method of manufacturing a semiconductor device, including forming an opening in an interlevel insulating film disposed on a semiconductor substrate, forming an auxiliary film containing a predetermined metal element, to cover an inner surface of the opening, forming a main film to fill the opening after forming the auxiliary film, the main film containing, as a main component, Cu used as a material of an interconnection main layer, and performing a heat treatment before or after forming the main film, thereby diffusing the predetermined metal element of the auxiliary film onto a surface of the interlevel insulating film facing the auxiliary film, so as to form a barrier film on the interlevel insulating film within the opening, the barrier film containing, as a main component, a compound of the predetermined metal element with a component element of the interlevel insulating film.Type: GrantFiled: April 14, 2011Date of Patent: March 13, 2012Assignee: Semiconductor Technology Academic Research CenterInventors: Junichi Koike, Makoto Wada, Shingo Takahashi, Noriyoshi Shimizu, Hideki Shibata, Satoshi Nishikawa, Takamasa Usui, Hayato Nasu, Masaki Yoshimaru
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Publication number: 20110189849Abstract: A method of manufacturing a semiconductor device, including forming an opening in an interlevel insulating film disposed on a semiconductor substrate, forming an auxiliary film containing a predetermined metal element, to cover an inner surface of the opening, forming a main film to fill the opening after forming the auxiliary film, the main film containing, as a main component, Cu used as a material of an interconnection main layer, and performing a heat treatment before or after forming the main film, thereby diffusing the predetermined metal element of the auxiliary film onto a surface of the interlevel insulating film facing the auxiliary film, so as to form a barrier film on the interlevel insulating film within the opening, the barrier film containing, as a main component, a compound of the predetermined metal element with a component element of the interlevel insulating film.Type: ApplicationFiled: April 14, 2011Publication date: August 4, 2011Applicant: SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTERInventors: Junichi KOIKE, Makoto Wada, Shingo Takahashi, Noriyoshi Shimizu, Hideki Shibata, Satoshi Nishikawa, Takamasa Usui, Hayato Nasu, Masaki Yoshimaru
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Patent number: 7943517Abstract: A method of manufacturing a semiconductor device, including forming an opening in an interlevel insulating film disposed on a semiconductor substrate, forming an auxiliary film containing a predetermined metal element, to cover an inner surface of the opening, forming a main film to fill the opening after forming the auxiliary film, the main film containing, as a main component, Cu used as a material of an interconnection main layer, and performing a heat treatment before or after forming the main film, thereby diffusing the predetermined metal element of the auxiliary film onto a surface of the interlevel insulating film facing the auxiliary film, so as to form a barrier film on the interlevel insulating film within the opening, the barrier film containing, as a main component, a compound of the predetermined metal element with a component element of the interlevel insulating film.Type: GrantFiled: October 23, 2007Date of Patent: May 17, 2011Assignee: Semiconductor Technology Academic Research CenterInventors: Junichi Koike, Makoto Wada, Shingo Takahashi, Noriyoshi Shimizu, Hideki Shibata, Satoshi Nishikawa, Takamasa Usui, Hayato Nasu, Masaki Yoshimaru
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Publication number: 20110097890Abstract: A method of fabricating a semiconductor device according to an embodiment includes: forming a precursor film containing therein a predetermined metallic element on a surface of a recess portion formed in an insulating film on a semiconductor substrate; forming a wiring formation film on the precursor film; performing a heat treatment in an oxidation ambient atmosphere to cause the precursor film and the insulating film to react with each other, thereby forming a self-formed barrier film containing a compound, containing therein the predetermined metallic element and a constituent element of the insulating film, as a basic constituent in a boundary surface between the precursor film and the insulating film, and moving the predetermined metallic element unreacted into the wiring formation film through diffusion to cause the predetermined metallic element unreacted to react with oxygen contained in the oxidation ambient atmosphere on a surface of the wiring formation film, thereby precipitating an unreacted metaType: ApplicationFiled: January 3, 2011Publication date: April 28, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takamasa USUI, Tadayoshi WATANABE, Hayato NASU
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Patent number: 7902068Abstract: In one aspect of the present invention, a method of fabricating a semiconductor device may include forming a sacrificial film on a substrate, forming an insulating film on the sacrificial film, forming a plurality of first openings in the sacrificial film and the insulating film in a first region and a second region, depositing a conductive material in the plurality of the first openings, forming a second opening in the insulating film in the second region so as to expose the sacrificial film, and removing the sacrificial film in the first region via the second opening in the second region.Type: GrantFiled: December 19, 2007Date of Patent: March 8, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Tadayoshi Watanabe, Yoshiaki Shimooka, Naofumi Nakamura, Hayato Nasu
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Patent number: 7888253Abstract: A method of fabricating a semiconductor device according to an embodiment includes: forming a precursor film containing therein a predetermined metallic element on a surface of a recess portion formed in an insulating film on a semiconductor substrate; forming a wiring formation film on the precursor film; performing a heat treatment in an oxidation ambient atmosphere to cause the precursor film and the insulating film to react with each other, thereby forming a self-formed barrier film containing a compound, containing therein the predetermined metallic element and a constituent element of the insulating film, as a basic constituent in a boundary surface between the precursor film and the insulating film, and moving the predetermined metallic element unreacted into the wiring formation film through diffusion to cause the predetermined metallic element unreacted to react with oxygen contained in the oxidation ambient atmosphere on a surface of the wiring formation film, thereby precipitating an unreacted metaType: GrantFiled: December 14, 2007Date of Patent: February 15, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Takamasa Usui, Tadayoshi Watanabe, Hayato Nasu
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Patent number: 7786523Abstract: A transistor formed on a semiconductor substrate has a gate electrode formed via a gate insulating film and first and second diffusion layers formed in the semiconductor substrate, the first and second diffusion layers being positioned at both sides of the gate electrode. A first electrode is connected to the first diffusion layer of the transistor. A capacitor insulating film formed on the first electrode is formed of a silicon oxide film containing a substrate which is faster than Cu in diffusion velocity and which more readily reacts with oxygen than Cu does. A second electrode formed on the capacitor insulating film is formed of one of a Cu layer and another Cu layer containing the substance.Type: GrantFiled: November 16, 2009Date of Patent: August 31, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Yumi Hayashi, Hayato Nasu, Kazumichi Tsumura, Takamasa Usui, Hiroyoshi Tanimoto
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Publication number: 20100052028Abstract: A transistor formed on a semiconductor substrate has a gate electrode formed via a gate insulating film and first and second diffusion layers formed in the semiconductor substrate, the first and second diffusion layers being positioned at both sides of the gate electrode. A first electrode is connected to the first diffusion layer of the transistor. A capacitor insulating film formed on the first electrode is formed of a silicon oxide film containing a substrate which is faster than Cu in diffusion velocity and which more readily reacts with oxygen than Cu does. A second electrode formed on the capacitor insulating film is formed of one of a Cu layer and another Cu layer containing the substance.Type: ApplicationFiled: November 16, 2009Publication date: March 4, 2010Inventors: Yumi HAYASHI, Hayato Nasu, Kazumichi Tsumura, Takamasa Usui, Hiroyoshi Tanimoto
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Patent number: 7638829Abstract: A transistor formed on a semiconductor substrate has a gate electrode formed via a gate insulating film and first and second diffusion layers formed in the semiconductor substrate, the first and second diffusion layers being positioned at both sides of the gate electrode. A first electrode is connected to the first diffusion layer of the transistor. A capacitor insulating film formed on the first electrode is formed of a silicon oxide film containing a substrate which is faster than Cu in diffusion velocity and which more readily reacts with oxygen than Cu does. A second electrode formed on the capacitor insulating film is formed of one of a Cu layer and another Cu layer containing the substance.Type: GrantFiled: May 12, 2006Date of Patent: December 29, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Yumi Hayashi, Hayato Nasu, Kazumichi Tsumura, Takamasa Usui, Hiroyoshi Tanimoto
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Patent number: 7485915Abstract: A semiconductor device includes a capacitor which includes a capacitor insulating film at least including a first insulating film and a ferroelectric film formed in contact with the first insulating film, containing a compound of a preset metal element and a constituent element of the first insulating film as a main component and having a dielectric constant larger than that of the first insulating film, a first capacitor electrode formed of one of Cu and a material containing Cu as a main component, and a second capacitor electrode formed to sandwich the capacitor insulating film in cooperation with the first capacitor electrode.Type: GrantFiled: May 5, 2006Date of Patent: February 3, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Hayato Nasu, Takamasa Usui, Hideki Shibata
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Publication number: 20080311742Abstract: In one aspect of the present invention, a method of fabricating a semiconductor device may include forming a sacrificial film on a substrate, forming an insulating film on the sacrificial film, forming a plurality of first openings in the sacrificial film and the insulating film in a first region and a second region, depositing a conductive material in the plurality of the first openings, forming a second opening in the insulating film in the second region so as to expose the sacrificial film, and removing the sacrificial film in the first region via the second opening in the second region.Type: ApplicationFiled: December 19, 2007Publication date: December 18, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tadayoshi WATANABE, Yoshiaki Shimooka, Naofumi Nakamura, Hayato Nasu
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Publication number: 20080146015Abstract: A method of fabricating a semiconductor device according to an embodiment includes: forming a precursor film containing therein a predetermined metallic element on a surface of a recess portion formed in an insulating film on a semiconductor substrate; forming a wiring formation film on the precursor film; performing a heat treatment in an oxidation ambient atmosphere to cause the precursor film and the insulating film to react with each other, thereby forming a self-formed barrier film containing a compound, containing therein the predetermined metallic element and a constituent element of the insulating film, as a basic constituent in a boundary surface between the precursor film and the insulating film, and moving the predetermined metallic element unreacted into the wiring formation film through diffusion to cause the predetermined metallic element unreacted to react with oxygen contained in the oxidation ambient atmosphere on a surface of the wiring formation film, thereby precipitating an unreacted metaType: ApplicationFiled: December 14, 2007Publication date: June 19, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takamasa USUI, Tadayoshi WATANABE, Hayato NASU
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Publication number: 20080057704Abstract: A method of manufacturing a semiconductor device, including forming an opening in an interlevel insulating film disposed on a semiconductor substrate, forming an auxiliary film containing a predetermined metal element, to cover an inner surface of the opening, forming a main film to fill the opening after forming the auxiliary film, the main film containing, as a main component, Cu used as a material of an interconnection main layer, and performing a heat treatment before or after forming the main film, thereby diffusing the predetermined metal element of the auxiliary film onto a surface of the interlevel insulating film facing the auxiliary film, so as to form a barrier film on the interlevel insulating film within the opening, the barrier film containing, as a main component, a compound of the predetermined metal element with a component element of the interlevel insulating film.Type: ApplicationFiled: October 23, 2007Publication date: March 6, 2008Applicant: SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTERInventors: Junichi Koike, Makoto Wada, Shingo Takahashi, Noriyoshi Shimizu, Hideki Shibata, Satoshi Nishikawa, Takamasa Usui, Hayato Nasu, Masaki Yoshimaru
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Publication number: 20080054466Abstract: In one aspect of the invention, a method of manufacturing a semiconductor device may include providing a first dielectric layer, providing a trench in the first dielectric layer and a wiring layer which has a Cu in the trench, providing a cap layer on a top surface of the wiring layer, the cap layer being conductive and having a Co, and providing a Cu silicide nitride layer on a part of the top surface of the wiring layer, on which the cap layer is not provided.Type: ApplicationFiled: August 31, 2007Publication date: March 6, 2008Applicant: Kabushiki Kaisha ToshibaInventors: Hayato NASU, Akihiro Kajita, Yumi Hayashi, Takamasa Usui, Kazumichi Tsumura
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Patent number: 7304384Abstract: A semiconductor device includes an interlevel insulating film disposed on a semiconductor substrate and having an opening formed therein. An interconnection main layer, which contains Cu as a main component, is embedded in the opening. A barrier film is interposed between the interlevel insulating film and the interconnection main layer within the opening. The barrier film contains, as a main component, a compound of a predetermined metal element with a component element of the interlevel insulating film.Type: GrantFiled: February 24, 2005Date of Patent: December 4, 2007Assignee: Semiconductor Technology Academic Research CenterInventors: Junichi Koike, Makoto Wada, Shingo Takahashi, Noriyoshi Shimizu, Hideki Shibata, Satoshi Nishikawa, Takamasa Usui, Hayato Nasu, Masaki Yoshimaru
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Publication number: 20070262468Abstract: A semiconductor device includes a first semiconductor chip having a first pad, a bonding member having a second pad facing the first pad, and a refractory metal layer which is formed by electroless plating in direct contact with the first pad and the second pad.Type: ApplicationFiled: July 10, 2006Publication date: November 15, 2007Inventors: Hayato Nasu, Takamasa Usui
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Publication number: 20070170483Abstract: A transistor formed on a semiconductor substrate has a gate electrode formed via a gate insulating film and first and second diffusion layers formed in the semiconductor substrate, the first and second diffusion layers being positioned at both sides of the gate electrode. A first electrode is connected to the first diffusion layer of the transistor. A capacitor insulating film formed on the first electrode is formed of a silicon oxide film containing a substrate which is faster than Cu in diffusion velocity and which more readily reacts with oxygen than Cu does. A second electrode formed on the capacitor insulating film is formed of one of a Cu layer and another Cu layer containing the substance.Type: ApplicationFiled: May 12, 2006Publication date: July 26, 2007Inventors: Yumi Hayashi, Hayato Nasu, Kazumichi Tsumura, Takamasa Usui, Hiroyoshi Tanimoto
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Publication number: 20070012973Abstract: A semiconductor device includes a capacitor which includes a capacitor insulating film at least including a first insulating film and a ferroelectric film formed in contact with the first insulating film, containing a compound of a preset metal element and a constituent element of the first insulating film as a main component and having a dielectric constant larger than that of the first insulating film, a first capacitor electrode formed of one of Cu and a material containing Cu as a main component, and a second capacitor electrode formed to sandwich the capacitor insulating film in cooperation with the first capacitor electrode.Type: ApplicationFiled: May 5, 2006Publication date: January 18, 2007Inventors: Hayato Nasu, Takamasa Usui, Hideki Shibata